Xilinx VC709 User Manual page 31

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Table 1-19
Table 1-9: GTH Interface Connections to the FPGA (U1)
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
• Contains 4 GTH transceivers for PCIe lanes 4–7
Quad 115:
• MGTREFCLK0 - No clock
• MGTREFCLK1 - PCIe edge connector clock
• Contains 4 GTH transceivers for PCIe lanes 0–3
Quad 117:
• MGTREFCLK0 - No clock
• MGTREFCLK1 - No clock
• Contains 2 GTH transceivers for FMC1 HPC (DP8–DP9)
Quad 118:
• MGTREFCLK0 - FMC1 HPC GBTCLK1
• MGTREFCLK1 - FMC1 HPC GBTCLK0
• Contains 4 GTH transceivers for FMC1 HPC (DP4–DP7)
Quad 119:
• MGTREFCLK0 - No clock
• MGTREFCLK1 - No clock
• Contains 4 GTH transceivers for FMC1 HPC (DP0–DP3)
lists the GTH interface connections to the FPGA (U1).
Transceiver Bank
MGT_BANK_113
MGT_BANK_114
MGT_BANK_115
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Net Name
GTHE2_CHANNEL_X1Y15
GTHE2_CHANNEL_X1Y14
GTHE2_CHANNEL_X1Y13
GTHE2_CHANNEL_X1Y12
MGTREFCLK0
MGTREFCLK1
GTHE2_CHANNEL_X1Y19
GTHE2_CHANNEL_X1Y18
GTHE2_CHANNEL_X1Y17
GTHE2_CHANNEL_X1Y16
MGTREFCLK0
MGTREFCLK1
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y20
MGTREFCLK0
Feature Descriptions
Connections
SFP/SFP+ 4
SFP/SFP+ 3
SFP/SFP+ 2
SFP/SFP+ 1
Si5324 jitter attenuator
SMA_MGT_REFCLK
PCIe4
PCIe5
PCIe6
PCIe7
NC
NC
PCIe0
PCIe1
PCIe2
PCIe3
NC
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