Xilinx VC709 User Manual page 63

X-Ref Target - Figure 1-28
U3
P28F00AG18FE
1Gb Flash Memory
RST_B
CLK
WE_B
OE_B
ADV_B
NC
A27
A[26:01]
D[15:00]
CE_B
WAIT
(VCC, VCCQ, 1.8V)
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
SW9
Part of
GND
SW11
Mode
Switch
1.8V
Part of
SW11
A25
A24
FLASH_A[25:0]
U40
Oscillator
80 MHz
Figure 1-28: VC709 Board Configuration Circuit
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U1
FPGA
PROG_B
Bank 0
(VCCO = 1.8V)
M[2:0]
INIT_B
DONE
CCLK
FWE_B
FOE_B
ADV_B
RS1
RS0
Bank 15
(VCCO = 1.8V)
GND
NC
A[26:25]
A[23:16]
A[15:00]
D[15:00]
Bank 14
(VCCO = 1.8V)
FCS_B
RDWR_B
EMCCLK
Configuration Options
TCK
TMS
TDI
TDO
1.8V
261Ω
3.3V
DS10
GREEN
R396
261Ω
Q15
NDS331N
460 mW
GND
UG887_c1_28_090612
63