Xilinx VC709 User Manual page 73

VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
## GPIO LEDS
## Bank 15 VCCO = 1.8V
## Active high to illuminate
##
#############################################
NET GPIO_LED_0_LS LOC = AM39 ; # DS2
NET GPIO_LED_1_LS LOC = AN39 ; # DS3
NET GPIO_LED_2_LS LOC = AR37 ; # DS4
NET GPIO_LED_3_LS LOC = AT37 ; # DS5
NET GPIO_LED_4_LS LOC = AR35 ; # DS6
NET GPIO_LED_5_LS LOC = AP41 ; # DS7
NET GPIO_LED_6_LS LOC = AP42 ; # DS8
NET GPIO_LED_7_LS LOC = AU39 ; # DS9
#############################################
##
## GPIO Pushbutton Switches
## Bank 15 VCCO = 1.8V
## Active high to illuminate
##
#############################################
NET GPIO_SW_N LOC = AR40 ; # SW3
NET GPIO_SW_S LOC = AP40 ; # SW5
NET GPIO_SW_C LOC = AV39 ; # SW6
NET GPIO_SW_E LOC = AU38 ; # SW4
NET GPIO_SW_W LOC = AW40 ; # SW7
NET CPU_RESET LOC = AV40 ; # SW8
#############################################
##
## FPGA PMBUS Interface
## Bank 15 VCCO = 1.8V
## Signals tie into PMBus connector J5
##
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NET PMBUS_ALERT_LS LOC = AV38 ; J5-8
NET PMBUS_CLK_LS LOC = AW37 ; J5-9
NET PMBUS_DATA_LS LOC = AY39 ; J5-10
#############################################
##
## FPGA Fan Interface
## Bank 15 VCCO = 1.8V
## Fan connector J48 (12V fan)
##
#############################################
NET SM_FAN_PWM LOC = BA37 ; FPGA output
NET SM_FAN_TACH LOC = BB37 ; J48-3 (FPGA input)
#############################################
##
## DDR3 SODIMM Interface "A"
## Board Socket J1 (left side of FPGA)
## Part Number: MT8KTF51264HZ-1G9E1 (single rank)
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VC709 Board UCF Listing
73