Xilinx VC709 User Manual page 86

Appendix C: Master UCF Listing
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##
NET SFP[4]_TX_P
NET SFP[4]_TX_N
NET SFP[3]_TX_N
NET SFP[3]_TX_P
NET SFP[2]_TX_P
NET SFP[2]_TX_N
NET SFP[1]_TX_P
NET SFP[1]_TX_N
##
## SFP+ Receiver Lanes
##
NET SFP[4]_RX_P
NET SFP[4]_RX_N
NET SFP[3]_RX_P
NET SFP[3]_RX_N
NET SFP[2]_RX_P
NET SFP[2]_RX_N
NET SFP[1]_RX_P
NET SFP[1]_RX_N
##
## SFP+ GTH reference clock inputs:
##
NET SI5324_OUT_C_P
NET SI5324_OUT_C_N
NET SMA_MGT_REFCLK_N
NET SMA_MGT_REFCLK_P
#############################################
##
## SFP+ Control & Status I/O
## Bank 17 VCCO = 1.8V
## FPGA SFP I/O: 1.8V to 3.3V level shifters
## "netname_LS" is 1.8V FPGA side
##
## PCB has 4.7K pullups to 3.3V on SFP I/O
## at SFP connector ports.
##
## 1. FPGA INPUTS:
## A. TX_FAULT ( 1 = tranmitter fault )
## B. TX_LOS ( 1 = loss of signal )
## C. MOD_DETECT ( 0 = module present )
##
## 2. FPGA OUTPUTS:
## A. TX_DISABLE ( 1 = disable TX optics )
## B. RS0 ( 1 = full BW: rate select0 )
## ( 0 = half BW )
## C. RS1 ( tied to receiver GND: rate select1 )
## Force RS1 to GND from FPGA side.
##
#############################################
NET SFP1_TX_FAULT_LS
NET SFP1_LOS_LS
NET SFP1_MOD_DETECT_LS
NET SFP1_TX_DISABLE_LS_B
NET SFP1_RS0_LS
NET SFP1_RS1_LS
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LOC = AL2 ;# MGTXTXP3_113
LOC = AL1 ;# MGTXTXN3_113
LOC = AM3 ;# MGTXTXN2_113
LOC = AM4 ;# MGTXTXP2_113
LOC = AN2 ;# MGTXTXP1_113
LOC = AN1 ;# MGTXTXN1_113
LOC = AP4 ;# MGTXTXP0_113
LOC = AP3 ;# MGTXTXN0_113
LOC = AJ6 ;# MGTXRXP3_113
LOC = AJ5 ;# MGTXRXN3_113
LOC = AL6 ;# MGTXRXP2_113
LOC = AL5 ;# MGTXRXN2_113
LOC = AM8 ;# MGTXRXP1_113
LOC = AM7 ;# MGTXRXN1_113
LOC = AN6 ;# MGTXRXP0_113
LOC = AN5 ;# MGTXRXN0_113
LOC = AH8 ;# MGTREFCLK0P_113
LOC = AH7 ;# MGTREFCLK0N_113
LOC = AK7 ;# MGTREFCLK1N_113 SMA J25
LOC = AK8 ;# MGTREFCLK1P_113 SMA J26
LOC = Y38 ; # Input
LOC = Y39 ; # Input
LOC = AB42 ; # Input
LOC = AB41 ; # Output
LOC = W40 ; # Output
LOC = Y40 ; # Output
UG887 (v1.0) February 4, 2013
VC709 Evaluation Board