Xilinx VC709 User Manual page 32

Chapter 1: VC709 Evaluation Board Features
Table 1-9: GTH Interface Connections to the FPGA (U1) (Cont'd)
For more information on the GTH transceivers see 7 Series FPGAs GTX/GTH Transceivers
User Guide (UG476).
32
Transceiver Bank
MGT_BANK_117
MGT_BANK_118
MGT_BANK_119
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Net Name
MGTREFCLK1
GTHE2_CHANNEL_X1Y31
GTHE2_CHANNEL_X1Y30
GTHE2_CHANNEL_X1Y29
GTHE2_CHANNEL_X1Y28
MGTREFCLK0
MGTREFCLK1
GTHE2_CHANNEL_X1Y35
GTHE2_CHANNEL_X1Y34
GTHE2_CHANNEL_X1Y33
GTHE2_CHANNEL_X1Y32
MGTREFCLK0
MGTREFCLK1
GTHE2_CHANNEL_X1Y39
GTHE2_CHANNEL_X1Y38
GTHE2_CHANNEL_X1Y37
GTHE2_CHANNEL_X1Y36
MGTREFCLK0
MGTREFCLK1
Connections
PCIe_CLK
NC
NC
FMC2 HPC DP8
FMC2 HPC DP9
NC
NC
FMC1 HPC DP7
FMC1 HPC DP6
FMC1 HPC DP5
FMC1 HPC DP4
FMC1 HPC GBT_CLK1
FMC2 HPC GBT_CLK0
FMC1 HPC DP3
FMC1 HPC DP2
FMC1 HPC DP1
FMC1 HPC DP0
NC
NC
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013