Xilinx VC709 User Manual page 10

Chapter 1: VC709 Evaluation Board Features
X-Ref Target - Figure 1-3
The default mode setting is M[2:0] = 010, which selects Master BPI at board power-on.
Refer to the
switch SW11.
Table 1-2: VC709 Board FPGA Configuration Modes
For full details on configuring the FPGA, see 7 Series FPGAs Configuration User Guide
(UG470).
I/O Voltage Rails
There are 17 I/O banks available on the Virtex-7 device. Fourteen I/O banks are available
on the VC709 board, and banks 12, 16, and 18 are not used. The voltages applied to the
FPGA I/O banks used by the VC709 board are listed in
Table 1-3: I/O Voltage Rails
10
ON Position = 1
Configuration Options, page 61
SW13 DIP Switch
Configuration Mode
Settings (M[2:0])
Master BPI
JTAG
FPGA (U1) Bank
Bank 0
Bank 12
Bank 13
Bank 14
Bank 15
Bank 16
Bank 17
Bank 18
Bank 19
Bank 31
Bank 32
Bank 33
Bank 34
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1 2 3 4 5
Figure 1-3: SW11 Default Settings
for detailed information about the mode
Bus Width
010
101
Power Supply Rail Net Name
VCC1V8_FPGA
NOT USED
VCC1V8_FPGA
VCC1V8_FPGA
VCC1V8_FPGA
NOT USED
VCC1V8_FPGA
NOT USED
VCC1V8_FPGA
VCC1V5_FPGA
VCC1V5_FPGA
VCC1V5_FPGA
VCC1V8_FPGA
OFF Position = 0
UG887_c1_03_083112
CCLK Direction
x8, x16 Output
x1 Not applicable
Table 1-3.
Voltage
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.5V
1.5V
1.5V
1.8V
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013