Xilinx VC709 User Manual page 25

Table 1-7: VC709 Board Clock Sources
Clock Name
Source
System clock
User clock
User SMA clock
(differential pair)
GTH SMA REF clock
(differential pair)
Jitter-attenuated clock
Memory clock
Table 1-8
Table 1-8: Clock Connections, Source to FPGA
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
Clock
SiT9102 2.5V LVDS 200 MHz fixed frequency oscillator (Si Time)
U51
See System Clock (SYSCLK_P and SYSCLK_N), page 26
2
Si570 3.3V LVDS I
default (Silicon Labs).
U34
See Programmable User Clock (USER_CLOCK_P and USER_CLOCK_N), page 26
USER_SMA_CLOCK_P (net name)
J31
See User SMA Clock (USER_SMA_CLOCK_P and USER_SMA_CLOCK_N), page 27
USER_SMA_CLOCK_N (net name)
J32
See User SMA Clock (USER_SMA_CLOCK_P and USER_SMA_CLOCK_N), page 27
SMA_MGT_REFCLK_C_P (net name)
J25
See GTH SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N),
page 28
SMA_MGT_REFCLK_C_N (net name)
J26
See GTH SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N),
page 28
Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs)
U24
See Jitter-Attenuated Clock, page 28
SiT9122 2.5V LVDS 233.33
U13
See Memory Clock (SYSCLK_233_P and SYSCLK_233_N), page
lists the pin-to-pin connections from each clock source to the FPGA.
Clock Source Pin
U51.5
U51.4
U34.5
U34.4
J26.1
J25.1
J32.1
J31.1
U24.29
U24.28
U13.5
U13.4
www.xilinx.com
Description
C Programmable Oscillator, (
MHz fixed frequency oscillator (Si Time).
Net Name
SYSCLK_N
SYSCLK_P
USER_CLOCK_N
USER_CLOCK_P
SMA_MGT_REFCLK_N
SMA_MGT_REFCLK_P
USER_SMA_CLOCK_N
USER_SMA_CLOCK_P
Si5324_OUT_N
Si5324_OUT_P
SYSCLK_233_N
SYSCLK_233_P
Feature Descriptions
2
I C address 0x5D), 156.250 MHz
29.
FPGA (U1) Pin
G18
H19
AL34
AK34
AK7
AK8
AK32
AJ32
AD7
AD8
AY17
AY18
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