Xilinx VC709 User Manual page 37

Table 1-12: GTH Quad 114 PCIe Edge Connector Connections (Cont'd)
Quad 114 Pin Name
MGTXTXN1_114_AJ1
MGTXRXP1_114_AF4
MGTXRXN1_114_AF3
MGTXTXP2_114_AH4
MGTXTXN2_114_AH3
MGTXRXP2_114_AE6
MGTXRXN2_114_AE5
MGTXTXP3_114_AG2
MGTXTXN3_114_AG1
MGTXRXP3_114_AD4
MGTXRXN3_114_AD3
MGTREFCLK0P_114_AD8
MGTREFCLK0N_114_AD7
MGTREFCLK1P_114_AF8
MGTREFCLK1N_114_AF7
For more information refer to 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
and 7 Series FPGAs Integrated Block for PCI Express User Guide (UG477).
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
FPGA
Net Name
(U1) Pin
AJ1 PCIE_TX6_N
AF4 PCIE_RX6_P
AF3 PCIE_RX6_N
AH4 PCIE_TX5_P
AH3 PCIE_TX5_N
AE6 PCIE_RX5_P
AE5 PCIE_RX5_N
AG2 PCIE_TX4_P
AG1 PCIE_TX4_N
AD4 PCIE_RX4_P
AD3 PCIE_RX4_N
AD8 NC
AD7 NC
AF8 NC
AF7 NC
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PCIe Edge Connector
(P1)
Pin Pin Name
A44 PERn6 GTHE2_CHANNEL_X1Y17
B41 PETp6 GTHE2_CHANNEL_X1Y17
B42 PETn6 GTHE2_CHANNEL_X1Y17
A39 PERp5 GTHE2_CHANNEL_X1Y18
A40 PERn5 GTHE2_CHANNEL_X1Y18
B37 PETp5 GTHE2_CHANNEL_X1Y18
B38 PETn5 GTHE2_CHANNEL_X1Y18
A35 PERp4 GTHE2_CHANNEL_X1Y19
A36 PERn4 GTHE2_CHANNEL_X1Y19
B33 PETp4 GTHE2_CHANNEL_X1Y19
B34 PETn4 GTHE2_CHANNEL_X1Y19
Feature Descriptions
FFG1761 Placement
MGT_BANK_114
MGT_BANK_114
MGT_BANK_114
MGT_BANK_114
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