Xilinx VC709 User Manual page 46

Chapter 1: VC709 Evaluation Board Features
Figure 1-19
X-Ref Target - Figure 1-19
GPIO_DIP_SW0
GPIO_DIP_SW1
GPIO_DIP_SW2
GPIO_DIP_SW3
GPIO_DIP_SW4
GPIO_DIP_SW5
GPIO_DIP_SW6
GPIO_DIP_SW7
1
2
R46
1
4.7K
1/10W
2
5%
GND
Table 1-19
Table 1-19: GPIO Connections to FPGA U1
Indicator LEDs (Active-High)
Directional Pushbutton Switches
8-Pole DIP Switch
46
shows the GPIO DIP switch circuit.
R47 R49
1
4.7K 4.7K
1/10W 1/10W
2
5% 5%
R48
1
4.7K
1/10W
2
5%
Figure 1-19: GPIO DIP Switch
lists the GPIO connections to FPGA U1.
FPGA (U1) Pin
AM39
AN39
AR37
AT37
AR35
AP41
AP42
AU39
AR40
AU38
AP40
AW40
AV39
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R52
1
4.7K
1/10W
2
5%
R53 R51
1 1
4.7K 4.7K
1/10W 1/10W
2 2
5% 5%
Schematic Net Name
GPIO_LED_0
GPIO_LED_1
GPIO_LED_2
GPIO_LED_3
GPIO_LED_4
GPIO_LED_5
GPIO_LED_6
GPIO_LED_7
GPIO_SW_N
GPIO_SW_E
GPIO_SW_S
GPIO_SW_W
GPIO_SW_C
VCC1V8
SDA08H1SBD
16 1
15 2
14 3
13 4
12 5
11 6
10 7
9 8
SW2
R50
1
4.7K
1/10W
2
5%
UG887_c1_19_011013
GPIO Pin
DS2.2
DS3.2
DS4.2
DS5.2
DS6.2
DS7.2
DS8.2
DS9.2
SW3.3
SW4.3
SW5.3
SW7.3
SW6.3
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013