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Chapter 1: VC709 Evaluation Board Features
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The VC709 board block diagram is shown in
6
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Gen2 8-lane (x8)
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Gen3 8-lane (x8)
4 X SFP+ connectors
USB-to-UART bridge
2
I
C bus
2
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I
C MUX
2
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I
C EEPROM (1 KB)
2
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USER I
C programmable LVDS oscillator
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2 X DDR3 SODIMM socket
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FMC HPC connector
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4 X SFP+ connector
2
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I
C programmable jitter-attenuating precision clock multiplier
Status LEDs
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12VDC power on
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TI controlled power good
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Linear power good
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FPGA INIT
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FPGA DONE
User I/O
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User LEDs (eight GPIO)
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User pushbuttons (five directional)
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CPU reset pushbutton
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User DIP switch (8-pole GPIO)
Switches
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Power on/off slide switch
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FPGA_PROG_B pushbutton
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Configuration mode DIP switch
VITA 57.1 FMC HPC connector
Power management
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PMBus voltage and current monitoring through TI power controllers
XADC header
Configuration options
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Linear BPI flash memory
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USB JTAG (Digilent) configuration port
Caution!
The VC709 board can be damaged by electrostatic discharge (ESD). Follow
standard ESD prevention measures when handling the board.
www.xilinx.com
Figure
1-1.
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
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