Xilinx VC709 User Manual page 77

VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
##
## DDR3 SODIMM Interface "B"
## Board Socket J3 (right side of FPGA)
## Part Number: MT8KTF51264HZ-1G9E1 (single rank)
## 1866 MT/s performance
## Must use 233.33333MHz clock for MIG design
## DDR3 FPGA VCCO = 1.5V
##
## Bank 31 = Data groups 7:4
## Bank 32 = Address & Control group
## Bank 33 = Data groups 3:0
##
############################################
##
## Bank 32 Address & Control
## DDR3 SODIMM B clocks and clock enables:
##
NET DDR3_B_CLK[1]_P
NET DDR3_B_CLK[1]_N
NET DDR3_B_CLK[0]_P
NET DDR3_B_CLK[0]_N
NET DDR3_B_CKE[1]
NET DDR3_B_CKE[0]
##
## DDR3 SODIMM B selects:
## S0 for rank 0
## S1 for rank 1
##
NET DDR3_B_S[1]_B
NET DDR3_B_S[0]_B
##
## DDR3 SODIMM B controls:
##
NET DDR3_B_RAS_B
NET DDR3_B_CAS_B
NET DDR3_B_WE_B
NET DDR3_B_ODT[1]
NET DDR3_B_ODT[0]
NET DDR3_B_RESET_B
NET DDR3_B_TEMP_EVENT_B
##
## DDR3 SODIMM B addresses:
##
NET DDR3_B_A[15]
NET DDR3_B_A[14]
NET DDR3_B_A[13]
NET DDR3_B_A[12]
NET DDR3_B_A[11]
NET DDR3_B_A[10]
NET DDR3_B_A[9]
NET DDR3_B_A[8]
NET DDR3_B_A[7]
NET DDR3_B_A[6]
NET DDR3_B_A[5]
NET DDR3_B_A[4]
NET DDR3_B_A[3]
NET DDR3_B_A[2]
NET DDR3_B_A[1]
NET DDR3_B_A[0]
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VC709 Board UCF Listing
LOC = AU18 ; # IO_L11P_T1_SRCC_32
LOC = AV18 ; # IO_L11N_T1_SRCC_32
LOC = AT17 ; # IO_L12P_T1_MRCC_32
LOC = AU17 ; # IO_L12N_T1_MRCC_32
LOC = AW18 ; # IO_L14P_T2_SRCC_32
LOC = AW17 ; # IO_L14N_T2_SRCC_32
LOC = AT19 ; # IO_L16N_T2_32
LOC = AV16 ; # IO_L17P_T2_32
LOC = AV19 ; # IO_L15N_T2_DQS_32
LOC = AT20 ; # IO_L16P_T2_32
LOC = AU19 ; # IO_L15P_T2_DQS_32
LOC = AW16 ; # IO_L17N_T2_32
LOC = AT16 ; # IO_L18P_T2_32
LOC = BB19 ; # IO_L19P_T3_32
LOC = AU16 ; # IO_L18N_T2_32
LOC = AL19 ; # IO_L1P_T0_32
LOC = AM19 ; # IO_L1N_T0_32
LOC = AK17 ; # IO_L2P_T0_32
LOC = AL17 ; # IO_L2N_T0_32
LOC = AM18 ; # IO_L3P_T0_DQS_32
LOC = AM17 ; # IO_L3N_T0_DQS_32
LOC = AK19 ; # IO_L4P_T0_32
LOC = AK18 ; # IO_L4N_T0_32
LOC = AM16 ; # IO_L5P_T0_32
LOC = AN16 ; # IO_L5N_T0_32
LOC = AJ18 ; # IO_L6P_T0_32
LOC = AP18 ; # IO_L7P_T1_32
LOC = AP17 ; # IO_L7N_T1_32
LOC = AP20 ; # IO_L8P_T1_32
LOC = AR19 ; # IO_L8N_T1_32
LOC = AN19 ; # IO_L9P_T1_DQS_32
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