Xilinx DK-V7-VC709-G User Manual page 94

Appendix C: Master Constraints File Listing
94
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set_property PACKAGE_PIN AA5 [get_ports PCIE_RX1_N]
set_property PACKAGE_PIN AA6 [get_ports PCIE_RX1_P]
set_property PACKAGE_PIN AB3 [get_ports PCIE_RX2_N]
set_property PACKAGE_PIN AB4 [get_ports PCIE_RX2_P]
set_property PACKAGE_PIN AC5 [get_ports PCIE_RX3_N]
set_property PACKAGE_PIN AC6 [get_ports PCIE_RX3_P]
set_property PACKAGE_PIN AD3 [get_ports PCIE_RX4_N]
set_property PACKAGE_PIN AD4 [get_ports PCIE_RX4_P]
set_property PACKAGE_PIN AE5 [get_ports PCIE_RX5_N]
set_property PACKAGE_PIN AE6 [get_ports PCIE_RX5_P]
set_property PACKAGE_PIN AF3 [get_ports PCIE_RX6_N]
set_property PACKAGE_PIN AF4 [get_ports PCIE_RX6_P]
set_property PACKAGE_PIN AG5 [get_ports PCIE_RX7_N]
set_property PACKAGE_PIN AG6 [get_ports PCIE_RX7_P]
set_property PACKAGE_PIN W1 [get_ports PCIE_TX0_N]
set_property PACKAGE_PIN W2 [get_ports PCIE_TX0_P]
set_property PACKAGE_PIN AA1 [get_ports PCIE_TX1_N]
set_property PACKAGE_PIN AA2 [get_ports PCIE_TX1_P]
set_property PACKAGE_PIN AC1 [get_ports PCIE_TX2_N]
set_property PACKAGE_PIN AC2 [get_ports PCIE_TX2_P]
set_property PACKAGE_PIN AE1 [get_ports PCIE_TX3_N]
set_property PACKAGE_PIN AE2 [get_ports PCIE_TX3_P]
set_property PACKAGE_PIN AG1 [get_ports PCIE_TX4_N]
set_property PACKAGE_PIN AG2 [get_ports PCIE_TX4_P]
set_property PACKAGE_PIN AH3 [get_ports PCIE_TX5_N]
set_property PACKAGE_PIN AH4 [get_ports PCIE_TX5_P]
set_property PACKAGE_PIN AJ1 [get_ports PCIE_TX6_N]
set_property PACKAGE_PIN AJ2 [get_ports PCIE_TX6_P]
set_property PACKAGE_PIN AK3 [get_ports PCIE_TX7_N]
set_property PACKAGE_PIN AK4 [get_ports PCIE_TX7_P]
set_property PACKAGE_PIN AV33 [get_ports PCIE_WAKE_B_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PCIE_WAKE_B_LS]
#PMBUS
set_property PACKAGE_PIN AV38 [get_ports PMBUS_ALERT_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PMBUS_ALERT_LS]
set_property PACKAGE_PIN AW37 [get_ports PMBUS_CLK_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PMBUS_CLK_LS]
set_property PACKAGE_PIN AY39 [get_ports PMBUS_DATA_LS]
set_property IOSTANDARD LVCMOS18 [get_ports PMBUS_DATA_LS]
#SFP1
set_property PACKAGE_PIN Y39 [get_ports SFP1_LOS_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SFP1_LOS_LS]
set_property PACKAGE_PIN AB42 [get_ports SFP1_MOD_DETECT_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SFP1_MOD_DETECT_LS]
set_property PACKAGE_PIN W40 [get_ports SFP1_RS0_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SFP1_RS0_LS]
set_property PACKAGE_PIN Y40 [get_ports SFP1_RS1_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SFP1_RS1_LS]
set_property PACKAGE_PIN AN5 [get_ports SFP1_RX_N]
set_property PACKAGE_PIN AN6 [get_ports SFP1_RX_P]
set_property PACKAGE_PIN AB41 [get_ports SFP1_TX_DISABLE_LS_B]
set_property IOSTANDARD LVCMOS18 [get_ports SFP1_TX_DISABLE_LS_B]
set_property PACKAGE_PIN Y38 [get_ports SFP1_TX_FAULT_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SFP1_TX_FAULT_LS]
set_property PACKAGE_PIN AP3 [get_ports SFP1_TX_N]
set_property PACKAGE_PIN AP4 [get_ports SFP1_TX_P]
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UG887 (v1.4) December 4, 2014