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Chapter 1: VC709 Evaluation Board Features
Table 1-6: BPI Flash Memory Connections to the FPGA (Cont'd)
FPGA (U1) Pin
AN36
AJ36
AJ37
AK37
AL37
AN35
AP35
AM37
AG33
AH33
AK35
AL35
AJ31
AH34
AJ35
AM34
BB41
BA41
N10
AL36
AY37
AG11
Additional FPGA bitstreams can be stored and used for configuration by setting the Warm
Boot Start Address (WBSTAR) register contained in 7 series FPGAs. More information is
available in the reconfiguration and multiboot section in 7 Series FPGAs Configuration
User Guide (UG470)
The configuration section of 7 Series FPGAs Configuration User Guide (UG470)
provides details on the Master BPI configuration mode.
24
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Net Name
I/O Standard
FLASH_D1
LVCMOS18
FLASH_D2
LVCMOS18
FLASH_D3
LVCMOS18
FLASH_D4
LVCMOS18
FLASH_D5
LVCMOS18
FLASH_D6
LVCMOS18
FLASH_D7
LVCMOS18
FLASH_D8
LVCMOS18
FLASH_D9
LVCMOS18
FLASH_D10
LVCMOS18
FLASH_D11
LVCMOS18
FLASH_D12
LVCMOS18
FLASH_D13
LVCMOS18
FLASH_D14
LVCMOS18
FLASH_D15
LVCMOS18
FLASH_WAIT
LVCMOS18
FPGA_FWE_B
LVCMOS18
FLASH_OE_B
LVCMOS18
FPGA_CCLK
LVCMOS18
FLASH_CE_B
LVCMOS18
FLASH_ADV_B
LVCMOS18
FPGA_INIT_B
LVCMOS18
[Ref
2].
www.xilinx.com
BPI Flash Memory (U3)
Pin Number
Pin Name
E2
G3
E4
E5
G5
G6
H7
E1
E3
F3
DQ10
F4
DQ11
F5
DQ12
H5
DQ13
G7
DQ14
E7
DQ15
F7
WAIT
G8
WE_B
F8
OE_B
E6
B4
F6
ADV_B
D4
RST_B
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
CLK
CE_B
[Ref 2]
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