Xilinx DK-V7-VC709-G User Manual page 42

Chapter 1: VC709 Evaluation Board Features
Table 1-12
Table 1-12: GTH Quad 114 PCIe Edge Connector Connections
Quad 114 Pin Name
MGTXTXP0_114_AK4
MGTXTXN0_114_AK3
MGTXRXP0_114_AG6
MGTXRXN0_114_AG5
MGTXTXP1_114_AJ2
MGTXTXN1_114_AJ1
MGTXRXP1_114_AF4
MGTXRXN1_114_AF3
MGTXTXP2_114_AH4
MGTXTXN2_114_AH3
MGTXRXP2_114_AE6
MGTXRXN2_114_AE5
MGTXTXP3_114_AG2
MGTXTXN3_114_AG1
MGTXRXP3_114_AD4
MGTXRXN3_114_AD3
MGTREFCLK0P_114_AD8
MGTREFCLK0N_114_AD7
MGTREFCLK1P_114_AF8
MGTREFCLK1N_114_AF7
The PCIe edge connector P1 has two LVCMOS18 signals connected to the XCVX690T
FPGA U1. The nets PCIE_PERST (P1.A11) and PCIE_WAKE_B (P1.B11) are level-shifted to
1.8V at U38, and are connected to the XCVX690T FPGA U1 bank 13 pins AV35 and AV33,
respectively.
For more information refer to 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
[Ref 5]
42
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lists the PCIe edge connector connections for Quad 114.
FPGA
Net Name
(U1) Pin
AK4 PCIE_TX7_P
AK3 PCIE_TX7_N
AG6 PCIE_RX7_P
AG5 PCIE_RX7_N
AJ2 PCIE_TX6_P
AJ1 PCIE_TX6_N
AF4 PCIE_RX6_P
AF3 PCIE_RX6_N
AH4 PCIE_TX5_P
AH3 PCIE_TX5_N
AE6 PCIE_RX5_P
AE5 PCIE_RX5_N
AG2 PCIE_TX4_P
AG1 PCIE_TX4_N
AD4 PCIE_RX4_P
AD3 PCIE_RX4_N
AD8 NC
AD7 NC
AF8 NC
AF7 NC
and 7 Series FPGAs Integrated Block for PCI Express User Guide (PG054)
www.xilinx.com
PCIe Edge Connector
(P1)
Pin Pin Name
A47 PERp7 GTHE2_CHANNEL_X1Y16
A48 PERn7 GTHE2_CHANNEL_X1Y16
B45 PETp7 GTHE2_CHANNEL_X1Y16
B46 PETn7 GTHE2_CHANNEL_X1Y16
A43 PERp6 GTHE2_CHANNEL_X1Y17
A44 PERn6 GTHE2_CHANNEL_X1Y17
B41 PETp6 GTHE2_CHANNEL_X1Y17
B42 PETn6 GTHE2_CHANNEL_X1Y17
A39 PERp5 GTHE2_CHANNEL_X1Y18
A40 PERn5 GTHE2_CHANNEL_X1Y18
B37 PETp5 GTHE2_CHANNEL_X1Y18
B38 PETn5 GTHE2_CHANNEL_X1Y18
A35 PERp4 GTHE2_CHANNEL_X1Y19
A36 PERn4 GTHE2_CHANNEL_X1Y19
B33 PETp4 GTHE2_CHANNEL_X1Y19
B34 PETn4 GTHE2_CHANNEL_X1Y19
UG887 (v1.4) December 4, 2014
FFG1761 Placement
MGT_BANK_114
MGT_BANK_114
MGT_BANK_114
MGT_BANK_114
[Ref 6].
VC709 Evaluation Board