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Multiple bitstreams can be stored in the linear BPI flash. The two most significant address
bits (A25, A24) of the flash memory are connected to DIP switch SW11 positions 1 and 2
respectively, and to the RS1 and RS0 pins of the FPGA. By placing valid XC7VX690T
bitstreams at four different offset addresses in the flash memory, 1 of the 4 bitstreams can
be selected to configure the FPGA by appropriately setting the DIP switch SW11. The
connections between the BPI flash memory and the FPGA are listed in
Table 1-6: BPI Flash Memory Connections to the FPGA
FPGA (U1) Pin
AJ28
AH28
AG31
AF30
AK29
AK28
AG29
AK30
AJ30
AH30
AH29
AL30
AL29
AN33
AM33
AM32
AV41
AU41
BA42
AU42
AT41
BA39
BA39
BB39
AW42
AW41
NA
AM36
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014
Net Name
I/O Standard
FLASH_A0
LVCMOS18
FLASH_A1
LVCMOS18
FLASH_A2
LVCMOS18
FLASH_A3
LVCMOS18
FLASH_A4
LVCMOS18
FLASH_A5
LVCMOS18
FLASH_A6
LVCMOS18
FLASH_A7
LVCMOS18
FLASH_A8
LVCMOS18
FLASH_A9
LVCMOS18
FLASH_A10
LVCMOS18
FLASH_A11
LVCMOS18
FLASH_A12
LVCMOS18
FLASH_A13
LVCMOS18
FLASH_A14
LVCMOS18
FLASH_A15
LVCMOS18
FLASH_A16
LVCMOS18
FLASH_A17
LVCMOS18
FLASH_A18
LVCMOS18
FLASH_A19
LVCMOS18
FLASH_A20
LVCMOS18
FLASH_A21
LVCMOS18
FLASH_A22
LVCMOS18
FLASH_A23
LVCMOS18
FLASH_A24
LVCMOS18
FLASH_A25
LVCMOS18
NC
FLASH_D0
LVCMOS18
www.xilinx.com
BPI Flash Memory (U3)
Pin Number
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
B8
NA
H1
F2
Feature Descriptions
Table
1-6.
Pin Name
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
DQ0
23
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