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Chapter 1: VC709 Evaluation Board Features
Table 1-17: I
EEPROM_IIC_SDA/SCL
PCA9546 (SFP1–SFP4)
NOT USED
IIC_SDA/SCL_DDR3 J1
IIC_SDA/SCL_DDR3 J3
Si5324_SDA/SCL
Notes:
1. Use the PCA9548 (U52) at
The U52 PCA9548 I2C bus MUX has three LVCMOS18 connections to the XCVC190T
FPGA U1.
•
•
•
Information about the PCA9546A and PCA9548A is available on the
website.
Status LEDs
[Figure
Table 1-18
Table 1-18: Status LEDs
Reference Designator
DS1
DS10
DS14
DS16
DS17
DS18
48
Send Feedback
2
C Bus Addresses (Cont'd)
2
I
C Bus
2
I
C
U52 pin 19 net IIC_SCL_MAIN is level-shifted to 1.8V by Q16 and is connected to U1
bank 13 pin AT35.
U52 pin 20 net IIC_SDA_MAIN is level-shifted to 1.8V by Q17 and is connected to U1
bank 13 pin AU32.
U52 pin 24 net IIC_MUX_RESET_B is level-shifted to 1.8V by U70 and is connected to
U1 bank 15 pin AY42. Both I2C switches U52 and U14 have a common reset net
IIC_MUX_RESET_B. This is an active-Low signal and must be driven High (FPGA U1
pin AY42) to enable I2C bus transactions between the FPGA U1 and the other
components on the I2C bus.
1-2, callout 24]
defines the status LEDs. For user-controlled LEDs, see
Signal Name
FPGA_INIT_B
FPGA_DONE
PWRCTL1_VCC4A_PG
VCC12_P_IN
PWRCTL_PWRGOOD
LINEAR_POWER_GOOD
www.xilinx.com
2
I
C Switch
Position
3
0b1010100
4
0b1110101
5
NOT USED
0b1010001, 0b0011001
6
0b1010010, 0b0011010
7
0b1101000
address 0x74 (0b01110100) to set up the path to these buses.
Color
GREEN: FPGA initialization successful
GREEN/RED
RED: FPGA initialization in progress or
configuration CRC failure
GREEN
FPGA configured successfully
GREEN
FMC1 HPC power good
GREEN
12V power ON
GREEN
TI power system power good
GREEN
DDR3 SODIMMs VTT power good
2
I
C Address
Texas Instruments
User I/O, page
49.
Description
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014
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