Xilinx DK-V7-VC709-G User Manual page 80

Appendix C: Master Constraints File Listing
80
Send Feedback
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS6_N]
set_property PACKAGE_PIN B28 [get_ports DDR3_A_DQS6_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS6_P]
set_property PACKAGE_PIN E28 [get_ports DDR3_A_DQS7_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS7_N]
set_property PACKAGE_PIN E27 [get_ports DDR3_A_DQS7_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS7_P]
set_property PACKAGE_PIN H20 [get_ports DDR3_A_ODT0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_ODT0]
set_property PACKAGE_PIN H18 [get_ports DDR3_A_ODT1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_ODT1]
set_property PACKAGE_PIN E20 [get_ports DDR3_A_RAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_RAS_B]
set_property PACKAGE_PIN P18 [get_ports DDR3_A_RESET_B]
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_A_RESET_B]
set_property PACKAGE_PIN J17 [get_ports DDR3_A_S0_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_S0_B]
set_property PACKAGE_PIN J20 [get_ports DDR3_A_S1_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_S1_B]
set_property PACKAGE_PIN G17 [get_ports DDR3_A_TEMP_EVENT_B]
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_A_TEMP_EVENT_B]
set_property PACKAGE_PIN F20 [get_ports DDR3_A_WE_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_WE_B]
#DDR3 SODIMM_B J3
set_property PACKAGE_PIN AN19 [get_ports DDR3_B_A0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A0]
set_property PACKAGE_PIN AR19 [get_ports DDR3_B_A1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A1]
set_property PACKAGE_PIN AP20 [get_ports DDR3_B_A2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A2]
set_property PACKAGE_PIN AP17 [get_ports DDR3_B_A3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A3]
set_property PACKAGE_PIN AP18 [get_ports DDR3_B_A4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A4]
set_property PACKAGE_PIN AJ18 [get_ports DDR3_B_A5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A5]
set_property PACKAGE_PIN AN16 [get_ports DDR3_B_A6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A6]
set_property PACKAGE_PIN AM16 [get_ports DDR3_B_A7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A7]
set_property PACKAGE_PIN AK18 [get_ports DDR3_B_A8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A8]
set_property PACKAGE_PIN AK19 [get_ports DDR3_B_A9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A9]
set_property PACKAGE_PIN AM17 [get_ports DDR3_B_A10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A10]
set_property PACKAGE_PIN AM18 [get_ports DDR3_B_A11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A11]
set_property PACKAGE_PIN AL17 [get_ports DDR3_B_A12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A12]
set_property PACKAGE_PIN AK17 [get_ports DDR3_B_A13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A13]
set_property PACKAGE_PIN AM19 [get_ports DDR3_B_A14]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A14]
set_property PACKAGE_PIN AL19 [get_ports DDR3_B_A15]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A15]
set_property PACKAGE_PIN AR17 [get_ports DDR3_B_BA0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_BA0]
www.xilinx.com VC709 Evaluation Board
UG887 (v1.4) December 4, 2014