Xilinx DK-V7-VC709-G User Manual page 21

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Table 1-5: DDR3 SODIMM Socket J3 Connections to the FPGA (Cont'd)
XCVX690T (U1) Pin
BB23
BB12
AV15
AK12
AP13
AP22
AP23
AK22
AJ22
AU21
AT21
BB22
BA22
BA14
BA15
AR12
AP12
AL14
AK15
AN14
AN15
AU17
AT17
AV18
AU18
AW17
AW18
AV19
AU19
AT20
AT16
AW16
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014
Net Name
DDR3_B_DM3
DDR3_B_DM4
DDR3_B_DM5
DDR3_B_DM6
DDR3_B_DM7
DDR3_B_DQS0_N
DDR3_B_DQS0_P
DDR3_B_DQS1_N
DDR3_B_DQS1_P
DDR3_B_DQS2_N
DDR3_B_DQS2_P
DDR3_B_DQS3_N
DDR3_B_DQS3_P
DDR3_B_DQS4_N
DDR3_B_DQS4_P
DDR3_B_DQS5_N
DDR3_B_DQS5_P
DDR3_B_DQS6_N
DDR3_B_DQS6_P
DDR3_B_DQS7_N
DDR3_B_DQS7_P
DDR3_B_CLK0_N
DDR3_B_CLK0_P
DDR3_B_CLK1_N
DDR3_B_CLK1_P
DDR3_B_CKE0
DDR3_B_CKE1
DDR3_B_RAS_B
DDR3_B_WE_B
DDR3_B_CAS_B
DDR3_B_ODT0
DDR3_B_ODT1
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DDR3 SODIMM Memory J3
I/O Standard
Pin Number
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
Feature Descriptions
Pin Name
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
10
DQS0_N
12
DQS0_P
27
DQS1_N
29
DQS1_P
45
DQS2_N
47
DQS2_P
62
DQS3_N
64
DQS3_P
135
DQS4_N
137
DQS4_P
152
DQS5_N
154
DQS5_P
169
DQS6_N
171
DQS6_P
186
DQS7_N
188
DQS7_P
101
CK0_P
103
CK0_N
102
CK1_P
104
CK1_N
73
CKE0
74
CKE1
110
RAS_B
113
WE_B
115
CAS_B
116
ODT0
120
ODT1
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