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Master Constraints File Listing
The VC709 board master Xilinx design constraints (XDC) file template provides for
designs targeting the VC709 board. Net names in the constraints listed in this appendix
correlate with net names on the latest VC709 board schematic. Users must identify the
appropriate pins and replace the net names listed here with net names in the user RTL. See
the Vivado Design Suite User Guide Using Constraints (UG903)
Users can refer to the XDC files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O
standards information required for each particular interface. The FMC connector J35 is
connected to 1.8V V
customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each
customer.
Note:
Virtex-7 FPGA VC709 Connectivity Kit Documentation website
file.
VC709 Board XDC Listing
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014
banks. Because each user's FMC card implements
CCO
The constraints file listed in this appendix might not be the latest version. Always refer to the
#SYSCLK
set_property PACKAGE_PIN G18 [get_ports SYSCLK_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports SYSCLK_N]
set_property PACKAGE_PIN H19 [get_ports SYSCLK_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports SYSCLK_P]
#SYSCLK_233
set_property PACKAGE_PIN AY17 [get_ports SYSCLK_233_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports SYSCLK_233_N]
set_property PACKAGE_PIN AY18 [get_ports SYSCLK_233_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports SYSCLK_233_P]
#USER CLOCK
set_property PACKAGE_PIN AL34 [get_ports USER_CLOCK_N]
set_property IOSTANDARD LVDS [get_ports USER_CLOCK_N]
set_property PACKAGE_PIN AK34 [get_ports USER_CLOCK_P]
set_property IOSTANDARD LVDS [get_ports USER_CLOCK_P]
#USER SMA CLOCK
set_property PACKAGE_PIN AK32 [get_ports USER_SMA_CLOCK_N]
set_property IOSTANDARD LVDS [get_ports USER_SMA_CLOCK_N]
set_property PACKAGE_PIN AJ32 [get_ports USER_SMA_CLOCK_P]
set_property IOSTANDARD LVDS [get_ports USER_SMA_CLOCK_P]
www.xilinx.com
Appendix C
[Ref 9]
for more information.
for the latest FPGA pins constraints
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