Xilinx DK-V7-VC709-G User Manual page 82

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Appendix C: Master Constraints File Listing
82
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set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D20]
set_property PACKAGE_PIN AV23 [get_ports DDR3_B_D21]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D21]
set_property PACKAGE_PIN AR24 [get_ports DDR3_B_D22]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D22]
set_property PACKAGE_PIN AT24 [get_ports DDR3_B_D23]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D23]
set_property PACKAGE_PIN BB24 [get_ports DDR3_B_D24]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D24]
set_property PACKAGE_PIN BA24 [get_ports DDR3_B_D25]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D25]
set_property PACKAGE_PIN AY23 [get_ports DDR3_B_D26]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D26]
set_property PACKAGE_PIN AY24 [get_ports DDR3_B_D27]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D27]
set_property PACKAGE_PIN AY25 [get_ports DDR3_B_D28]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D28]
set_property PACKAGE_PIN BA25 [get_ports DDR3_B_D29]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D29]
set_property PACKAGE_PIN BB21 [get_ports DDR3_B_D30]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D30]
set_property PACKAGE_PIN BA21 [get_ports DDR3_B_D31]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D31]
set_property PACKAGE_PIN AY14 [get_ports DDR3_B_D32]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D32]
set_property PACKAGE_PIN AW15 [get_ports DDR3_B_D33]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D33]
set_property PACKAGE_PIN BB14 [get_ports DDR3_B_D34]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D34]
set_property PACKAGE_PIN BB13 [get_ports DDR3_B_D35]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D35]
set_property PACKAGE_PIN AW12 [get_ports DDR3_B_D36]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D36]
set_property PACKAGE_PIN AY13 [get_ports DDR3_B_D37]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D37]
set_property PACKAGE_PIN AY12 [get_ports DDR3_B_D38]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D38]
set_property PACKAGE_PIN BA12 [get_ports DDR3_B_D39]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D39]
set_property PACKAGE_PIN AU12 [get_ports DDR3_B_D40]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D40]
set_property PACKAGE_PIN AU13 [get_ports DDR3_B_D41]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D41]
set_property PACKAGE_PIN AT12 [get_ports DDR3_B_D42]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D42]
set_property PACKAGE_PIN AU14 [get_ports DDR3_B_D43]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D43]
set_property PACKAGE_PIN AV13 [get_ports DDR3_B_D44]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D44]
set_property PACKAGE_PIN AW13 [get_ports DDR3_B_D45]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D45]
set_property PACKAGE_PIN AT15 [get_ports DDR3_B_D46]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D46]
set_property PACKAGE_PIN AR15 [get_ports DDR3_B_D47]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D47]
set_property PACKAGE_PIN AL15 [get_ports DDR3_B_D48]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D48]
set_property PACKAGE_PIN AJ15 [get_ports DDR3_B_D49]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D49]
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VC709 Evaluation Board
UG887 (v1.4) December 4, 2014

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