Xilinx DK-V7-VC709-G User Manual page 40

Chapter 1: VC709 Evaluation Board Features
Table 1-10: PCIe Edge Connector Connections (Cont'd)
Net Name FPGA (U1) Pin
PCIE_TX1_P AA2
PCIE_TX1_N AA1
PCIE_TX2_P
PCIE_TX2_N
PCIE_TX3_P
PCIE_TX3_N
PCIE_TX4_P AG2
PCIE_TX4_N AG1
PCIE_TX5_P AH4
PCIE_TX5_N AH3
PCIE_TX6_P
PCIE_TX6_N
PCIE_TX7_P
PCIE_TX7_N
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
PCIE_PRSNT_B J49 2, 4, 6
40
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PCIe Edge
Connector (P1)
Pin Name
A21 PERp1
A22 PERn1
AC2 A25 PERp2
AC1 A26 PERn2
AE2 A29 PERp3
AE1 A30 PERn3
A35 PERp4
A36 PERn4
A39 PERp5
A40 PERn5
AJ2 A43 PERp6
AJ1 A44 PERn6
AK4 A47 PERp7
AK3 A48 PERn7
AB8 A13 REFCLK+
AB7 A14 REFCLK-
A1 PRSNT#1
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Function
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
differential clock pair
from PCIe
Integrated Endpoint block
differential clock pair
from PCIe
J49 Lane Size Select
jumper
FFG1761 Placement
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y19
GTHE2_CHANNEL_X1Y19
GTHE2_CHANNEL_X1Y18
GTHE2_CHANNEL_X1Y18
GTHE2_CHANNEL_X1Y17
GTHE2_CHANNEL_X1Y17
GTHE2_CHANNEL_X1Y16
GTHE2_CHANNEL_X1Y16
MGT_BANK_115
MGT_BANK_115
NA
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014