Xilinx DK-V7-VC709-G User Manual page 41

Table 1-10: PCIe Edge Connector Connections (Cont'd)
Net Name FPGA (U1) Pin
PCIE_WAKE_B AV33
PCIE_PERST_B AV35
Table 1-11
Table 1-11: GTH Quad 115 PCIe Edge Connector Connections
Quad 115 Pin Name
MGTXTXP0_115_AE2
MGTXTXN0_115_AE1
MGTXRXP0_115_AC6
MGTXRXN0_115_AC5
MGTXTXP1_115_AC2
MGTXTXN1_115_AC1
MGTXRXP1_115_AB4
MGTXRXN1_115_AB3
MGTXTXP2_115_AA2
MGTXTXN2_115_AA1
MGTXRXP2_115_AA6
MGTXRXN2_115_AA5
MGTXTXP3_115_W2
MGTXTXN3_115_W1
MGTXRXP3_115_Y4
MGTXRXN3_115_Y3
MGTREFCLK0P_115_Y8
MGTREFCLK0N_115_Y7
MGTREFCLK1P_115_AB8
MGTREFCLK1N_115_AB7
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014
PCIe Edge
Connector (P1)
Pin Name
B11 WAKE#
A11 PERST
lists the PCIe edge connector connections for Quad 115.
FPGA
Net Name
(U1) Pin
AE2 PCIE_TX3_P
AE1 PCIE_TX3_N
AC6 PCIE_RX3_P
AC5 PCIE_RX3_N
AC2 PCIE_TX2_P
AC1 PCIE_TX2_N
AB4 PCIE_RX2_P
AB3 PCIE_RX2_N
AA2 PCIE_TX1_P
AA1 PCIE_TX1_N
AA6 PCIE_RX1_P
AA5 PCIE_RX1_N
W2 PCIE_TX0_P
W1 PCIE_TX0_N
Y4 PCIE_RX0_P
Y3 PCIE_RX0_N
Y8 NC
Y7 NC
AB8 PCIE_CLK_Q0_N
AB7 PCIE_CLK_Q0_P
www.xilinx.com
Function
Integrated Endpoint block
wake signal
Integrated Endpoint block
reset signal
PCIe Edge Connector
(P1)
Pin Pin Name
A29 PERp3
A30 PERn3
B27 PETp3
B28 PETn3
A25 PERp2
A26 PERn2
B23 PETp2
B24 PETn2
A21 PERp1
A22 PERn1
B19 PETp1
B20 PETn1
A16 PERp0
A17 PERn0
B14 PETp0
B15 PETn0
A13 REFCLK-
A14 REFCLK+
Feature Descriptions
FFG1761 Placement
U1 FPGA Bank13 Pin AV33
U1 FPGA Bank13 Pin AV35
FFG1761 Placement
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y23
MGT_BANK_115
MGT_BANK_115
MGT_BANK_115
MGT_BANK_115
Send Feedback
41