Xilinx DK-V7-VC709-G User Manual page 84

Appendix C: Master Constraints File Listing
84
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set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS3_P]
set_property PACKAGE_PIN BA14 [get_ports DDR3_B_DQS4_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS4_N]
set_property PACKAGE_PIN BA15 [get_ports DDR3_B_DQS4_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS4_P]
set_property PACKAGE_PIN AR12 [get_ports DDR3_B_DQS5_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS5_N]
set_property PACKAGE_PIN AP12 [get_ports DDR3_B_DQS5_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS5_P]
set_property PACKAGE_PIN AL14 [get_ports DDR3_B_DQS6_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS6_N]
set_property PACKAGE_PIN AK15 [get_ports DDR3_B_DQS6_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS6_P]
set_property PACKAGE_PIN AN14 [get_ports DDR3_B_DQS7_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS7_N]
set_property PACKAGE_PIN AN15 [get_ports DDR3_B_DQS7_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS7_P]
set_property PACKAGE_PIN AT16 [get_ports DDR3_B_ODT0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_ODT0]
set_property PACKAGE_PIN AW16 [get_ports DDR3_B_ODT1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_ODT1]
set_property PACKAGE_PIN AV19 [get_ports DDR3_B_RAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_RAS_B]
set_property PACKAGE_PIN BB19 [get_ports DDR3_B_RESET_B]
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_B_RESET_B]
set_property PACKAGE_PIN AV16 [get_ports DDR3_B_S0_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_S0_B]
set_property PACKAGE_PIN AT19 [get_ports DDR3_B_S1_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_S1_B]
set_property PACKAGE_PIN AU16 [get_ports DDR3_B_TEMP_EVENT_B]
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_B_TEMP_EVENT_B]
set_property PACKAGE_PIN AU19 [get_ports DDR3_B_WE_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_WE_B]
#BPI FLASH
set_property PACKAGE_PIN AJ28 [get_ports FLASH_A0]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A0]
set_property PACKAGE_PIN AH28 [get_ports FLASH_A1]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A1]
set_property PACKAGE_PIN AG31 [get_ports FLASH_A2]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A2]
set_property PACKAGE_PIN AF30 [get_ports FLASH_A3]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A3]
set_property PACKAGE_PIN AK29 [get_ports FLASH_A4]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A4]
set_property PACKAGE_PIN AK28 [get_ports FLASH_A5]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A5]
set_property PACKAGE_PIN AG29 [get_ports FLASH_A6]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A6]
set_property PACKAGE_PIN AK30 [get_ports FLASH_A7]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A7]
set_property PACKAGE_PIN AJ30 [get_ports FLASH_A8]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A8]
set_property PACKAGE_PIN AH30 [get_ports FLASH_A9]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A9]
set_property PACKAGE_PIN AH29 [get_ports FLASH_A10]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A10]
set_property PACKAGE_PIN AL30 [get_ports FLASH_A11]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_A11]
www.xilinx.com VC709 Evaluation Board
UG887 (v1.4) December 4, 2014