Xilinx DK-V7-VC709-G User Manual page 78

Appendix C: Master Constraints File Listing
78
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set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D25]
set_property PACKAGE_PIN B16 [get_ports DDR3_A_D26]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D26]
set_property PACKAGE_PIN D15 [get_ports DDR3_A_D27]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D27]
set_property PACKAGE_PIN D13 [get_ports DDR3_A_D28]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D28]
set_property PACKAGE_PIN E12 [get_ports DDR3_A_D29]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D29]
set_property PACKAGE_PIN C16 [get_ports DDR3_A_D30]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D30]
set_property PACKAGE_PIN D16 [get_ports DDR3_A_D31]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D31]
set_property PACKAGE_PIN A24 [get_ports DDR3_A_D32]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D32]
set_property PACKAGE_PIN B23 [get_ports DDR3_A_D33]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D33]
set_property PACKAGE_PIN B27 [get_ports DDR3_A_D34]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D34]
set_property PACKAGE_PIN B26 [get_ports DDR3_A_D35]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D35]
set_property PACKAGE_PIN A22 [get_ports DDR3_A_D36]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D36]
set_property PACKAGE_PIN B22 [get_ports DDR3_A_D37]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D37]
set_property PACKAGE_PIN A25 [get_ports DDR3_A_D38]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D38]
set_property PACKAGE_PIN C24 [get_ports DDR3_A_D39]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D39]
set_property PACKAGE_PIN E24 [get_ports DDR3_A_D40]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D40]
set_property PACKAGE_PIN D23 [get_ports DDR3_A_D41]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D41]
set_property PACKAGE_PIN D26 [get_ports DDR3_A_D42]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D42]
set_property PACKAGE_PIN C25 [get_ports DDR3_A_D43]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D43]
set_property PACKAGE_PIN E23 [get_ports DDR3_A_D44]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D44]
set_property PACKAGE_PIN D22 [get_ports DDR3_A_D45]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D45]
set_property PACKAGE_PIN F22 [get_ports DDR3_A_D46]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D46]
set_property PACKAGE_PIN E22 [get_ports DDR3_A_D47]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D47]
set_property PACKAGE_PIN A30 [get_ports DDR3_A_D48]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D48]
set_property PACKAGE_PIN D27 [get_ports DDR3_A_D49]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D49]
set_property PACKAGE_PIN A29 [get_ports DDR3_A_D50]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D50]
set_property PACKAGE_PIN C28 [get_ports DDR3_A_D51]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D51]
set_property PACKAGE_PIN D28 [get_ports DDR3_A_D52]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D52]
set_property PACKAGE_PIN B31 [get_ports DDR3_A_D53]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D53]
set_property PACKAGE_PIN A31 [get_ports DDR3_A_D54]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D54]
www.xilinx.com VC709 Evaluation Board
UG887 (v1.4) December 4, 2014