Xilinx DK-V7-VC709-G User Manual page 76

Appendix C: Master Constraints File Listing
76
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#SMA MGT REFCLK
set_property PACKAGE_PIN AK7 [get_ports SMA_MGT_REFCLK_N]
set_property PACKAGE_PIN AK8 [get_ports SMA_MGT_REFCLK_P]
#SI5324 REC_CLOCK
set_property PACKAGE_PIN AW33 [get_ports REC_CLOCK_C_N]
set_property IOSTANDARD LVDS [get_ports REC_CLOCK_C_N]
set_property PACKAGE_PIN AW32 [get_ports REC_CLOCK_C_P]
set_property IOSTANDARD LVDS [get_ports REC_CLOCK_C_P]
#FPGA EMCCLK
set_property PACKAGE_PIN AP37 [get_ports FPGA_EMCCLK]
set_property IOSTANDARD LVCMOS18 [get_ports FPGA_EMCCLK]
#DDR3 SODIMM_A J1
set_property PACKAGE_PIN A20 [get_ports DDR3_A_A0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A0]
set_property PACKAGE_PIN B19 [get_ports DDR3_A_A1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A1]
set_property PACKAGE_PIN C20 [get_ports DDR3_A_A2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A2]
set_property PACKAGE_PIN A19 [get_ports DDR3_A_A3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A3]
set_property PACKAGE_PIN A17 [get_ports DDR3_A_A4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A4]
set_property PACKAGE_PIN A16 [get_ports DDR3_A_A5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A5]
set_property PACKAGE_PIN D20 [get_ports DDR3_A_A6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A6]
set_property PACKAGE_PIN C18 [get_ports DDR3_A_A7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A7]
set_property PACKAGE_PIN D17 [get_ports DDR3_A_A8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A8]
set_property PACKAGE_PIN C19 [get_ports DDR3_A_A9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A9]
set_property PACKAGE_PIN B21 [get_ports DDR3_A_A10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A10]
set_property PACKAGE_PIN B17 [get_ports DDR3_A_A11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A11]
set_property PACKAGE_PIN A15 [get_ports DDR3_A_A12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A12]
set_property PACKAGE_PIN A21 [get_ports DDR3_A_A13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A13]
set_property PACKAGE_PIN F17 [get_ports DDR3_A_A14]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A14]
set_property PACKAGE_PIN E17 [get_ports DDR3_A_A15]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A15]
set_property PACKAGE_PIN D21 [get_ports DDR3_A_BA0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_BA0]
set_property PACKAGE_PIN C21 [get_ports DDR3_A_BA1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_BA1]
set_property PACKAGE_PIN D18 [get_ports DDR3_A_BA2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_BA2]
set_property PACKAGE_PIN K17 [get_ports DDR3_A_CAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_CAS_B]
set_property PACKAGE_PIN K19 [get_ports DDR3_A_CKE0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_CKE0]
set_property PACKAGE_PIN J18 [get_ports DDR3_A_CKE1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_CKE1]
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UG887 (v1.4) December 4, 2014