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Chapter 1: VC709 Evaluation Board Features
For more details, see the
Figure
X-Ref Target - Figure 1-7
Programmable User Clock (USER_CLOCK_P and USER_CLOCK_N)
[Figure
The VC709 board has a programmable low-jitter 3.3V differential oscillator (U34)
connected to the FPGA MRCC inputs of bank 14. This USER_CLOCK_P and
USER_CLOCK_N clock signal pair are connected to FPGA U1 pins AK34 and AL34
respectively. On power-up, the user clock defaults to an output frequency of 156.250 MHz.
User applications can change the output frequency within the range of 10 MHz to
810 MHz through an I
its default frequency of 156.250 MHz.
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•
•
•
30
Send Feedback
Si Time
1-7.
Figure 1-7: System Clock Source
1-2, callout 6]
2
C interface. Power cycling the VC709 board reverts the user clock to
Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz – 810 MHz)
PPM frequency jitter: 50 ppm
Differential output
2
I
C address 0x5D
www.xilinx.com
SiT9102 data sheet. The system clock circuit is shown in
UG887_c1_07_011013
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014
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