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9 REAL-TIME CLOCK (RTCA)
RTCA provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the inter-
rupt controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set.
For more information on interrupt control, refer to the "Interrupt Controller" chapter.
9.6 Control Registers
RTC Control Register
Register name
Bit
RTCCTL
15
14–8 RTCTRM[6:0]
7
6
5
4
3
2
1
0
Bit 15
RTCTRMBSY
This bit indicates whether the theoretical regulation is currently executed or not.
1 (R):
Theoretical regulation is executing.
0 (R):
Theoretical regulation has finished (or not executed).
This bit goes 1 when a value is written to the RTCCTL.RTCTRM[6:0] bits. The theoretical regulation
takes up to 1 second for execution. This bit reverts to 0 automatically after the theoretical regulation
has finished execution.
Bits 14–8 RTCTRM[6:0]
Write the correction value for adjusting the 1 Hz frequency to these bits to execute theoretical regula-
tion. For a calculation method of correction value, refer to "Theoretical Regulation Function."
Notes: • When the RTCCTL.RTCTRMBSY bit = 1, the RTCCTL.RTCTRM[6:0] bits cannot be
rewritten.
• Writing 0x00 to the RTCCTL.RTCTRM[6:0] bits sets the RTCCTL.RTCTRMBSY bit to 1 as
well. However, no correcting operation is performed.
Bit 7
Reserved
Bit 6
RTCBSY
This bit indicates whether the counter is performing count-up operation or not.
1 (R):
In count-up operation
0 (R):
Idle (ready to rewrite real-time clock counter)
This bit goes 1 when performing 1-second count-up, +1 second correction, or 30-second correction. It
retains 1 for 1/256 second and then reverts to 0.
Bit 5
RTCHLD
This bit halts the count-up operation of the real-time clock counter.
1 (R/W): Halt real-time clock counter count-up operation
0 (R/W): Normal operation
Writing 1 to this bit halts the count-up operation of the real-time clock counter, this makes it possible
to read the counter value correctly without changing the counter. Write 0 to this bit to resume count-
up operation immediately after the counter has been read. Depending on these operation timings, the
+1 second correction may be executed after the count-up operation resumes. For more information on
the +1 second correction, refer to "Real-Time Clock Counter Operations."
9-6
Bit name
Initial
RTCTRMBSY
0
0x00
–
0
RTCBSY
0
RTCHLD
0
RTC24H
0
–
0
RTCADJ
0
RTCRST
0
RTCRUN
0
Seiko Epson Corporation
Reset
R/W
H0
R
–
H0
W
Read as 0x00.
–
R
–
H0
R
H0
R/W
Cleared by setting the
RTCCTL.RTCRST bit to 1.
H0
R/W
–
–
R
H0
R/W
Cleared by setting the
RTCCTL.RTCRST bit to 1.
H0
R/W
–
H0
R/W
S1C17W03/W04 TECHNICAL MANUAL
Remarks
(Rev. 1.2)
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