Epson S1C17W03 Technical Manual page 40

2 POWER SUPPLY, RESET, AND CLOCKS
Bit 15 WUPMD
This bit enables the SYSCLK switching function at wake-up.
1 (R/WP): Enable
0 (R/WP): Disable
When the CLGSCLK.WUPMD bit = 1, setting values of the CLGSCLK.WUPSRC[1:0] bits and the
CLGSCLK.WUPDIV[1:0] bits are loaded to the CLGSCLK.CLKSRC[1:0] bits and the CLGSCLK.
CLKDIV[1:0] bits, respectively, at wake-up from SLEEP mode to switch SYSCLK. When the CLG-
SCLK.WUPMD bit = 0, the CLGSCLK.CLKSRC[1:0] and CLGSCLK.CLKDIV[1:0] bits are not
altered at wake-up.
Note: When the CLGSCLK.WUPMD bit = 1, the clock source enable bits (CLGOSC.EXOSCEN,
CLGOSC.OSC1EN, CLGOSC.OSC3EN, CLGOSC.IOSCEN) except for the SYSCLK source
selected by the CLGSCLK.CLKSRC[1:0] bits will be cleared to 0 to stop the clocks after a
system wake-up. However, the enable bit of the clock source being operated during SLEEP
mode by setting the CLGOSC.****SLPC bit retains 1 after a wake-up.
Bit 14 Reserved
Bits 13–12 WUPDIV[1:0]
These bits select the SYSCLK division ratio for resetting the CLGSCLK.CLKDIV[1:0] bits at wake-up.
This setting is ineffective when the CLGSCLK.WUPMD bit = 0.
Bits 11–10 Reserved
Bits 9–8 WUPSRC[1:0]
These bits select the SYSCLK clock source for resetting the CLGSCLK.CLKSRC[1:0] bits at wake-up.
When a currently stopped clock source is selected, it will automatically start oscillating or clock input
at wake-up. However, this setting is ineffective when the CLGSCLK.WUPMD bit = 0.
Table 2.6.3 SYSCLK Clock Source and Division Ratio Settings at Wake-up
CLGSCLK.
WUPDIV[1:0] bits
0x3
0x2
0x1
0x0
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits set the division ratio of the clock source to determine the SYSCLK frequency.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the SYSCLK clock source.
When a currently stopped clock source is selected, it will automatically start oscillating or clock input.
CLGSCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
2-18
0x0
IOSCCLK
1/8
1/4
1/2
1/1
Table 2.6.4 SYSCLK Clock Source and Division Ratio Settings
0x0
IOSCCLK
1/8
1/4
1/2
1/1
Seiko Epson Corporation
CLGSCLK.WUPSRC[1:0] bits
0x1 0x2
OSC1CLK OSC3CLK
Reserved 1/16
Reserved 1/8
1/2
1/2
1/1
1/1
CLGSCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1CLK OSC3CLK
Reserved 1/16
Reserved 1/8
1/2
1/2
1/1
1/1
S1C17W03/W04 TECHNICAL MANUAL
0x3
EXOSCCLK
Reserved
Reserved
Reserved
1/1
0x3
EXOSCCLK
Reserved
Reserved
Reserved
1/1
(Rev. 1.2)