Snda Select Register - Epson S1C17W03 Technical Manual

16 SOUND GENERATOR (SNDA)
Bits 6–4 CLKDIV[2:0]
These bits select the division ratio of the SNDA operating clock.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of SNDA.
SNDCLK.
CLKDIV[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note: The SNDCLK register settings can be altered only when the SNDCTL.MODEN bit = 0.

SNDA Select Register

Register name Bit
SNDSEL 15–12 –
11–8 STIM[3:0]
7–3 –
2
1–0 MOSEL[1:0]
Bits 15–12 Reserved
Bits 11–8 STIM[3:0]
These bits select a tempo (when melody mode is selected) or a one-shot buzzer output duration (when
one-shot buzzer mode is selected).
Table 16.6.2 Tempo/One-shot Buzzer Output Duration Selections (when f
Note: Be sure to avoid altering these bits when SNDINTF.SBSY bit = 1.
Bits 7–3 Reserved
16-10
Table 16.6.1 Clock Source and Division Ratio Settings
0x0
IOSC
Reserved
1/128
1/64
1/32
1/16
1/8
1/4
Bit name Initial
0x0
0x0
0x00
SINV 0
0x0
SNDSEL.
STIM[3:0] bits (= Quarter note/minute)
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko Epson Corporation
SNDCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
1/1 Reserved
1/128
1/64
1/32
1/16
1/8
1/4
Reset R/W
– R –
H0 R/W
– R
H0 R/W
H0 R/W
Tempo One-shot buzzer output
duration [ms]
30 250.0
32 234.4
34.3 218.8
36.9 203.1
40 187.5
43.6 171.9
48 156.3
53.3 140.6
60 125.0
68.6 109.4
80 93.8
96 78.1
120 62.5
160 46.9
240 31.3
480 15.6
0x3
EXOSC
1/1
Remarks
= 32,768 Hz)
CLK_SNDA
S1C17W03/W04 TECHNICAL MANUAL
(Rev. 1.2)