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4.3.2 Flash Bus Access Cycle Setting
There is a limit of frequency to access the Flash memory with no wait cycle, therefore, the number of bus access
cycles for reading must be changed according to the system clock frequency. The number of bus access cycles for
reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than
the system clock.
4.3.3 Flash Programming
The Flash memory supports on-board programming, so it can be programmed with the ROM data by using the de-
bugger through an ICDmini. Figure 4.3.3.1 shows a connection diagram for on-board programming.
The V
pin must be left open except when programming the Flash memory. However, it is not necessary to discon-
PP
nect the wire when using ICDmini to supply the V
it will be supplied during Flash programming only. When supplying the V
for stabilizing the V
voltage.
PP
For detailed information on ROM data programming method, refer to the "(S1C17 Family C Compiler Package)
S5U1C17001C Manual." The IC can also be shipped after being programmed in the factory with the ROM data
developed. Should you desire to ship the IC with ROM data programmed from the factory, please contact our cus-
tomer support.
Note: The Flash programming requires a 1.8 V or higher V
4.4 RAM
The RAM can be used to execute the instruction codes copied from another memory as well as storing variables or
other data. This allows higher speed processing and lower power consumption than Flash memory.
Note: The 64 bytes at the end of the RAM is reserved as the debug RAM area. When using the debug
functions under application development, do not access this area from the application program.
This area can be used for applications of mass-produced devices that do not need debugging.
The RAM size used by the application can be configured to equal or less than the implemented size using the
MSCIRAMSZ.IRAMSZ[2:0] bits. For example, this function can be used to prevent creating programs that seek
to access areas outside the RAM area of the target model when developing an application for a model in which the
RAM size is smaller than this IC. After the limitation is applied, accessing an address outside the RAM area results
in the same operation (undefined value is read out) as when a reserved area is accessed.
4.5 Peripheral Circuit Control Registers
The control registers for the peripheral circuits are located in the 8K-byte area beginning with address 0x4000.
Table 4.5.1 shows the control register map. For details of each control register, refer to "List of Peripheral Circuit
Registers" in the appendix or "Control Registers" in each peripheral circuit chapter.
S1C17W03/W04 TECHNICAL MANUAL
(Rev. 1.2)
DCLK
DCLK
V
DD
S1C17
R
DBG
DSIO
DSIO
DST2
DST2
V
Flash V
PP
C
VPP
Figure 4.3.3.1 External Connection
power source, as ICDmini controls the power supply so that
PP
Seiko Epson Corporation
ICDmini
(S5U1C17001H)
OUT
CC
power source, be sure to connect C
PP
voltage.
DD
4 MEMORY AND BUS
VPP
4-3
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