Reading Operation Results - Epson S1C17W03 Technical Manual

Conditions to set the overflow (V) flag
An overflow occurs in a signed MAC operation and the overflow (V) flag is set to 1 when the signs of the mul-
tiplication result, operation result register value, and multiplication & accumulation result match the following
conditions:
Mode setting value
0x07
0x07
An overflow occurs when a MAC operation performs addition of positive values and a negative value results,
or it performs addition of negative values and a positive value results. The coprocessor holds the operation re-
sult until the overflow (V) flag is cleared.
Conditions to clear the overflow (V) flag
The overflow (V) flag that has been set will be cleared when an overflow has not been occurred during execu-
tion of the "ld.ca" instruction for MAC operation or when the "ld.ca" or "ld.cf" instruction is executed
in an operation mode other than operation result read mode.

20.6 Reading Operation Results

The "ld.ca" instruction cannot load a 32-bit operation result to a CPU register, so a multiplication, division or
MAC operation returns the one-half (16 bits according to the output mode) result (A[15:0] or A[31:16]) and the
flag status to the CPU registers. Another one-half should be read by setting COPRO2 into operation result read
mode. The operation result register keeps the loaded operation result until it is rewritten by other operation.
S1C17 Core
Mode set-
Instruction
ting value
ld.ca %rd,%rs
0x03
ld.ca %rd,imm7 %rd ← res[15:0]
ld.ca %rd,%rs
0x13
ld.ca %rd,imm7 %rd ← res[31:16]
ld.ca %rd,%rs
0x23
ld.ca %rd,imm7 %rd ← res1[15:0]
ld.ca %rd,%rs
0x33
ld.ca %rd,imm7 %rd ← res1[31:16]
S1C17W03/W04 TECHNICAL MANUAL
(Rev. 1.2)
Table 20.5.3 Conditions to Set the Overflow (V) Flag
Sign of multiplication result
0 (positive)
1 (negative)
COPRO2
Argument 2
Argument 1
Operation result
Coprocessor
output (16 bits)
Flag output
Figure 20.6.1 Data Path in Operation Result Read Mode
Table 20.6.1 Operation in Operation Result Read Mode
Operations
%rd ← res[15:0]
%rd ← res[31:16]
%rd ← res1[15:0]
%rd ← res1[31:16]
res0: operation result register 0, res1: operation result register 1
Seiko Epson Corporation
20 Multiplier/Divider (COPRO2)
Sign of operation result
register value
0 (positive)
1 (negative)
16 bits
Operation result
register 1 register 0
Selector
Flags
psr (CVZN) ← 0b0000 This operation mode does not
Sign of multiplication &
accumulation result
1 (negative)
0 (positive)
Remarks
affect the operation result reg-
isters 0 and 1.
20-7