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APPENDIX C MOUNTING PRECAUTIONS
(2) If a bypass capacitor is connected between V
tions between the V
Signal line location
• To prevent electromagnetically-induced noise arising from mutual induc-
tion, large-current signal lines should not be positioned close to pins sus-
ceptible to noise, such as oscillator and analog measurement pins.
• Locating signal lines in parallel over significant distances or crossing
signal lines operating at high speed will cause malfunctions due to noise
generated by mutual interference.
Handling of light (for bare chip mounting)
The characteristics of semiconductor components can vary when exposed to light. ICs may malfunction or non-
volatile memory data may be corrupted if ICs are exposed to light.
Consider the following precautions for circuit boards and products in which this IC is mounted to prevent IC
malfunctions attributable to light exposure.
(1) Design and mount the product so that the IC is shielded from light during use.
(2) Shield the IC from light during inspection processes.
(3) Shield the IC on the upper, underside, and side faces of the IC chip.
(4) Mount the IC chip within one week of opening the package. If the IC chip must be stored before mounting,
take measures to ensure light shielding.
(5) Adequate evaluations are required to assess nonvolatile memory data retention characteristics before prod-
uct delivery if the product is subjected to heat stress exceeding regular reflow conditions during mounting
processes.
Unused pins
(1) I/O port (P) pins
Unused pins should be left open. The control registers should be fixed at the initial status.
(2) OSC1, OSC2, OSC3, OSC4, and EXOSC pins
If the OSC1 oscillator circuit, OSC3 oscillator circuit or EXOSC input circuit is not used, the OSC1 and
OSC2 pins, the OSC3 and OSC4 pins, or the EXOSC pin should be left open. The control registers should
be fixed at the initial status (disabled).
(3) C
and V
pins
V1–2
D2
If super economy mode is not used, the C
omitted by connecting between the V
C
is required even if super economy mode is not used.
PW3
(4) VREFA0 pin
If the 12-bit A/D converter is not used, the VREFA0 pin should be left open.
Treatment of exposed die pad
The exposed die pad of the packages such as QFN has the same potential as that of the substrate on the back of
the IC. When mounting these packages on a circuit board, please note the following:
(1) When soldering exposed die pad to mounting board
Connect the exposed die pad with a wiring pattern that has the same potential as the substrate potential
on the back of the IC, or do not connect it electrically (leave it open electrically). Even if connected to the
same potential on the back of the IC, the power supply pins must be connected to the power source (the ex-
posed die pad cannot be used as a power supply pad).
(2) When not soldering exposed die pad to mounting board
Do not place any signal wiring pattern on the exposed die pad area of the mounting board.
AP-C-2
/V
and V
pins should be as short as possible.
DD
DDA
SS
V1
and V
DD
Seiko Epson Corporation
/V
and V
, connec-
DD
DDA
SS
and C
pins should be left open. In this case, C
V2
pins directly. When these pins are not short-circuited,
D2
Bypass capacitor connection example
V
DD
(V
)
DDA
V
SS
C
C
PW1
PW1
(C
)
(C
)
PW4
PW4
Prohibited pattern
Large current signal line
High-speed signal line
PW3
S1C17W03/W04 TECHNICAL MANUAL
V
DD
(V
)
DDA
V
SS
OSC1
OSC2
can be
(Rev. 1.2)
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