Table Of Contents - Epson S1C17W03 Technical Manual

Cmos 16-bit single chip microcontroller
Table of Contents

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CONTENTS
Preface ......................................................................................................................................i
Notational conventions and symbols in this manual ................................................................i
1 Overview ........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram ................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 Pin Configuration Diagram (Package) ............................................................... 1-4
1.3.2 Pad Configuration Diagram (Chip) .................................................................... 1-6
1.3.3 Pin Descriptions ................................................................................................ 1-7
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWG2) ................................................................................................ 2-1
2.1.1 Overview ........................................................................................................... 2-1
2.1.2 Pins ................................................................................................................... 2-1
2.1.3 Operations ........................................................................................................ 2-2
2.2 System Reset Controller (SRC) ....................................................................................... 2-4
2.2.1 Overview ........................................................................................................... 2-4
2.2.2 Input Pin ............................................................................................................ 2-4
2.2.3 Reset Sources .................................................................................................. 2-4
2.2.4 Initialization Conditions (Reset Groups) ............................................................ 2-5
2.3 Clock Generator (CLG) .................................................................................................... 2-6
2.3.1 Overview ........................................................................................................... 2-6
2.3.2 Input/Output Pins ............................................................................................. 2-7
2.3.3 Clock Sources .................................................................................................. 2-7
2.3.4 Operations ........................................................................................................ 2-9
2.4 Operating Mode ............................................................................................................. 2-14
2.4.1 Initial Boot Sequence ....................................................................................... 2-14
2.4.2 Transition between Operating Modes .............................................................. 2-14
2.5 Interrupts ........................................................................................................................ 2-16
2.6 Control Registers ........................................................................................................... 2-16
PWG2 Control Register ............................................................................................................ 2-16
PWG2 Timing Control Register ................................................................................................ 2-17
PWG2 Interrupt Flag Register .................................................................................................. 2-17
PWG2 Interrupt Enable Register .............................................................................................. 2-17
CLG System Clock Control Register ........................................................................................ 2-17
CLG Oscillation Control Register ............................................................................................. 2-19
CLG IOSC Control Register ..................................................................................................... 2-19
CLG OSC1 Control Register .................................................................................................... 2-20
CLG OSC3 Control Register .................................................................................................... 2-21
CLG Interrupt Flag Register ..................................................................................................... 2-23
CLG Interrupt Enable Register ................................................................................................. 2-23
CLG FOUT Control Register ..................................................................................................... 2-24
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU Core ........................................................................................................................ 3-2
3.2.1 CPU Registers .................................................................................................. 3-2
3.2.2 Instruction Set .................................................................................................. 3-2
3.2.3 Reading PSR .................................................................................................... 3-2
3.2.4 I/O Area Reserved for the S1C17 Core ............................................................ 3-2
3.3 Debugger ........................................................................................................................ 3-2
ii
- Contents -
Seiko Epson Corporation
S1C17W03/W04 TECHNICAL MANUAL
(Rev. 1.2)

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