Table of Contents
Advertisement
12 UART (UART)
Bit 9
RBSY
This bit indicates the receiving status. (See Figure 12.5.3.1.)
1 (R):
During receiving
0 (R):
Idle
Bit 8
TBSY
This bit indicates the sending status. (See Figure 12.5.2.1.)
1 (R):
During sending
0 (R):
Idle
Bit 7
Reserved
Bit 6
TENDIF
Bit 5
FEIF
Bit 4
PEIF
Bit 3
OEIF
Bit 2
RB2FIF
Bit 1
RB1FIF
Bit 0
TBEIF
These bits indicate the UART interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
The following shows the correspondence between the bit and interrupt:
UAnINTF.TENDIF bit: End-of-transmission interrupt
UAnINTF.FEIF bit:
UAnINTF.PEIF bit:
UAnINTF.OEIF bit:
UAnINTF.RB2FIF bit: Receive buffer two bytes full interrupt
UAnINTF.RB1FIF bit: Receive buffer one byte full interrupt
UAnINTF.TBEIF bit:
UART Ch.n Interrupt Enable Register
Register name
Bit
UAnINTE
15–8 –
7
6
5
4
3
2
1
0
Bits 15–7 Reserved
Bit 6
TENDIE
Bit 5
FEIE
Bit 4
PEIE
Bit 3
OEIE
Bit 2
RB2FIE
Bit 1
RB1FIE
Bit 0
TBEIE
These bits enable UART interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
12-12
Framing error interrupt
Parity error interrupt
Overrun error interrupt
Transmit buffer empty interrupt
Bit name
Initial
0x00
–
0
TENDIE
0
FEIE
0
PEIE
0
OEIE
0
RB2FIE
0
RB1FIE
0
TBEIE
0
Seiko Epson Corporation
Reset
R/W
–
R
–
–
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
S1C17W03/W04 TECHNICAL MANUAL
Remarks
(Rev. 1.2)
Advertisement
Table of Contents
