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Bits 7–4
SVDRE[3:0]
These bits enable/disable the reset issuance function when a low power supply voltage is detected.
0xa (R/WP):
Other than 0xa (R/WP): Disable (Generate interrupt)
For more information on the SVD reset issuance function, refer to "SVD Reset."
Bit 3
Reserved
Bits 2–1
SVDMD[1:0]
These bits select intermittent operation mode and its detection cycle.
Table 10.6.4 Intermittent Operation Mode Detection Cycle Selection
SVDCTL.SVDMD[1:0] bits
For more information on intermittent and continuous operation modes, refer to "SVD Operations."
Bit 0
MODEN
This bit enables/disables for the SVD circuit to operate.
1 (R/WP): Enable (Start detection operations)
0 (R/WP): Disable (Stop detection operations)
After this bit has been altered, wait until the value written is read out from this bit without subsequent
operations being performed.
Notes: • Writing 0 to the SVDCTL.MODEN bit resets the SVD hardware. However, the register values
set and the interrupt flag are not cleared. The SVDCTL.MODEN bit is actually set to 0 after
this processing has finished. If 1 is written to the SVDCTL.MODEN bit continuously without
waiting for the bit being read as 0 at this time, writing 0 may be ignored and a malfunction
may occur as the hardware restarts without resetting.
• The SVD internal circuit is initialized if the SVDCTL.SVDSC[1:0] bits, SVDCTL.SVDRE[3:0]
bits, or SVDCTL.SVDMD[1:0] bits are altered while SVD is in operation after 1 is written to the
SVDCTL.MODEN bit.
SVD Status and Interrupt Flag Register
Register name
Bit
SVDINTF
15–9 –
8
7–1 –
0
Bits 15–9 Reserved
Bit 8
SVDDT
The power supply voltage detection results can be read out from this bit.
1 (R):
Power supply voltage (V
0 (R):
Power supply voltage (V
Bits 7–1
Reserved
Bit 0
SVDIF
This bit indicates the low power supply voltage detection interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
S1C17W03/W04 TECHNICAL MANUAL
(Rev. 1.2)
Enable (Issue reset)
0x3
Intermittent operation mode (CLK_SVD/512)
0x2
Intermittent operation mode (CLK_SVD/256)
0x1
Intermittent operation mode (CLK_SVD/128)
0x0
Bit name
Initial
0x00
SVDDT
x
0x00
SVDIF
0
or EXSVD) < SVD detection voltage V
DD
or EXSVD) ≥ SVD detection voltage V
DD
Seiko Epson Corporation
10 SUPPLY VOLTAGE DETECTOR (SVD)
Operation mode (detection cycle)
Continuous operation mode
Reset
R/W
–
R
–
–
R
–
R
H1
R/W
Cleared by writing 1.
Remarks
SVD
SVD
10-7
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