Spia Ch.n Transmit Data Register; Spia Ch.n Receive Data Register; Spia Ch.n Interrupt Flag Register - Epson S1C17W03 Technical Manual

Bit 1 SFTRST
This bit issues software reset to SPIA.
1 (W): Issue software reset
0 (W): Ineffective
1 (R): Software reset is executing.
0 (R): Software reset has finished. (During normal operation)
Setting this bit resets the SPIA shift register and transfer bit counter. This bit is automatically cleared
after the reset processing has finished.
Bit 0 MODEN
This bit enables the SPIA operations.
1 (R/W): Enable SPIA operations (In master mode, the operating clock is supplied.)
0 (R/W): Disable SPIA operations (In master mode, the operating clock is stopped.)
Note: If the SPInCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being
sent/received cannot be guaranteed. When setting the SPInCTL.MODEN bit to 1 again after that,
be sure to write 1 to the SPInCTL.SFTRST bit as well.

SPIA Ch.n Transmit Data Register

Register name Bit
SPInTXD 15–0 TXD[15:0]
Bits 15–0 TXD[15:0]
Data can be written to the transmit data buffer through these bits.
In master mode, writing to these bits starts data transfer.
Transmit data can be written when the SPInINTF.TBEIF bit = 1 regardless of whether data is being
output from the SDOn pin or not.
Note that the upper data bits that exceed the data bit length configured by the SPInMOD.CHLN[3:0]
bits will not be output from the SDOn pin.
Note: Be sure to avoid writing to the SPInTXD register when the SPInINTF.TBEIF bit = 0. Otherwise,
transfer data cannot be guaranteed.

SPIA Ch.n Receive Data Register

Register name Bit
SPInRXD 15–0 RXD[15:0]
Bits 15–0 RXD[15:0]
The receive data buffer can be read through these bits. Received data can be read when the SPInINTF.
RBFIF bit = 1 regardless of whether data is being input from the SDIn pin or not. Note that the upper
bits that exceed the data bit length configured by the SPInMOD.CHLN[3:0] bits become 0.
Note: The SPInRXD.RXD[15:0] bits are cleared to 0x0000 when 1 is written to the SPInCTL.MODEN bit
or the SPInCTL.SFTRST bit.

SPIA Ch.n Interrupt Flag Register

Register name Bit
SPInINTF 15–8 –
7
6–4 –
3
2
1
0
S1C17W03/W04 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x0000
Bit name Initial
0x0000
Bit name Initial
0x00
BSY 0
0x0
OEIF 0
TENDIF 0
RBFIF 0
TBEIF 1
Seiko Epson Corporation
13 SYNCHRONOUS SERIAL INTERFACE (SPIA)
Reset R/W
H0 R/W –
Reset R/W
H0 R –
Reset R/W
– R –
H0 R
– R
H0/S0 R/W Cleared by writing 1.
H0/S0 R/W
H0/S0 R Cleared by reading the
SPInRXD register.
H0/S0 R Cleared by writing to the
SPInTXD register.
Remarks
Remarks
Remarks
13-13