Interrupts; Control Registers; Snda Clock Control Register - Epson S1C17W03 Technical Manual

SNDDAT.SFRQ[7:0] bits
0x83
0x7c
0x75
0x6e
0x68
0x62
0x5c
0x57
0x52
0x4e
0x49
0x45
0x41
0x3d
0x3a
0x37
0x33
0x30
0x2e
0x2b
0x29
0x26
0x24
0x22
0x20
0x1e

16.5 Interrupts

SNDA has a function to generate the interrupts shown in Table 16.5.1.
Interrupt
Sound buffer empty SNDINTF.EMIF
Sound output SNDINTF.EDIF
completion
SNDA provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the inter-
rupt controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set.
For more information on interrupt control, refer to the "Interrupt Controller" chapter.

16.6 Control Registers

SNDA Clock Control Register

Register name Bit
SNDCLK 15–9 –
8
7
6–4 CLKDIV[2:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the SNDA operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bit 7 Reserved
S1C17W03/W04 TECHNICAL MANUAL
(Rev. 1.2)
Table 16.5.1 SNDA Interrupt Function
Interrupt flag
When data in the sound buffer (SNDDAT regis-
ter) is transferred to the sound register or 1 is
written to the SNDCTL.SSTP bit
When a sound output has completed
Bit name Initial
0x00
DBRUN 0
– 0
0x0
0x0
0x0
Seiko Epson Corporation
Scale
B3
C4
C#4
D4
D#4
E4
F4
F#4
G4
G#4
A4
A#4
B4
C5
C#5
D5
D#5
E5
F5
F#5
G5
G#5
A5
A#5
B5
C6
Set condition
Reset R/W
– R –
H0 R/W
– R
H0 R/W
– R
H0 R/W
16 SOUND GENERATOR (SNDA)
Frequency [Hz]
248.24
262.14
277.69
295.21
312.08
330.99
352.34
372.36
394.80
414.78
442.81
468.11
496.48
528.52
555.39
585.14
630.15
668.73
697.19
744.73
780.19
840.21
885.62
936.23
992.97
1057.03
Clear condition
Writing to the SNDDAT
register
Writing 1 or writing to
the SNDDAT register
Remarks
16-9