Part 3.3: Sfp Interface - Alinx AX7A200 Manual

Xilinx artix-7 fpga
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ARTIX-7 FPGA Development Board AX7A200 User Manual
ETH_RXCTL
ETH_MDC
ETH_MDIO
ETH_RESET

Part 3.3: SFP Interface

The AX7A200 FPGA development board has two optical interfaces. Users
can purchase SFP optical modules (1.25G, 2.5G optical modules on the market)
and insert them into these two optical interfaces for optical data communication.
The two fiber interfaces are connected to the two RX/TX of the GNK
transceiver of the FPGA. The TX signal and the RX signal are connected to the
FPGA and the optical module through the DC blocking capacitor in differential
signal mode. The TX and RX data rates are up to each 6.6Gb/s per channel.
The reference clock for the GTX transceiver is provided by the 125Mhz
differential clock of AC7A200 FPGA core board.
Figure 3-3-1 detailed the schematic diagram of FPGA and fiber design
38 / 59
R19
N13
P14
R14
Figure 3-3-1: SFP Interface Schematic
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Receive data valid signal
MDIO Management Clock
MDIO Management Data
PHY Chip Reset Signal
https://www.amazon.com/alinx
rachel.zhou@aithtech.com

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