Part 2.8: Power Interface On The Core Board - Alinx AX7A200 Manual

ARTIX-7 FPGA Development Board AX7A200 User Manual
GND, +3.3V these six signals.
The JTAG interface J1 on AC7A200 FPGA core board uses a 6-pin
2.54mm pitch single-row test hole. If you need to use the JTAG connector to
debug on the core board, you need to solder a 6-pin single-row pin header.
Figure 2-7-2 shows the JTAG interface J1 on the AC7A200 FPGA core board.
Figure 2-7-2 JTAG Interface on Core Board

Part 2.8: Power Interface on the Core Board

In order to make the AC7A200 FPGA core board work alone, the core
board is reserved 2-pin power supply interface J2. If the user wants to debug
the function of the core board separately (without the carrier board), the
external device needs to provide +5V to supply power to the core board.
23 / 59
Figure 2-7-1: JTAG Interface Schematic
Amazon Store:
Sales Email:
https://www.amazon.com/alinx
rachel.zhou@aithtech.com