Alinx ARTIX-7 FPGA Manual
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Alinx ARTIX-7 FPGA Manual

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ARTIX-7 FPGA
Development Board
AC7100B
System on Module

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Summary of Contents for Alinx ARTIX-7 FPGA

  • Page 1 ARTIX-7 FPGA Development Board AC7100B System on Module...

  • Page 2: Version Record

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Version Record Version Date Release By Description Rev 1.0 2020-10-28 Rachel Zhou First Release 2 / 30 Amazon Store: https://www.amazon.com/alinx...

  • Page 3: Table Of Contents

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Table of Contents Version Record.......................2 Part 1: AC7100B Core Board Introduction............4 Part 2: FPGA Chip....................6 Part 3: Active Differential Crystal................ 8 Part 3.1: 200Mhz Active Differential clock..........8 Part 3.2: 148.5Mhz Active Differential Crystal..........9 Part 4: DDR3 DRAM...................

  • Page 4: Part 1: Ac7100B Core Board Introduction

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Part 1: AC7100B Core Board Introduction AC7100B (core board model, the same below) FPGA core board, it is based on XILINX's ARTIX-7 series 100T XC7A100T-2FGG484I. It is a high-performance core board with high speed, high bandwidth and high capacity.
  • Page 5 ARTIX-7 FPGA Development Board AX7C7100B User Manual Figure 1-1: AC7100B Core Board (Front View) Figure 1-2: AC7100B Core Board (Rear View) 5 / 30 Amazon Store: https://www.amazon.com/alinx...

  • Page 6: Part 2: Fpga Chip

    Xilinx's Artix-7 series. The speed grade is 2, and the temperature grade is industry grade. This model is a FGG484 package with 484 pins. Xilinx ARTIX-7 FPGA chip naming rules as below Figure 2-1: The Specific Chip Model Definition of ARTIX-7 Series...
  • Page 7 FPGA internal GTP transceiver, connected to 1.0V; VMGTAVTT is the termination voltage of the GTP transceiver, connected to 1.2V. The Artix-7 FPGA system requires that the power-up sequence be powered by VCCINT, then VCCBRAM, then VCCAUX, and finally VCCO. If VCCINT and VCCBRAM have the same voltage, they can be powered up at the same time.

  • Page 8: Part 3: Active Differential Crystal

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Part 3: Active Differential Crystal The AC7100B core board is equipped with two Sitime active differential crystals, one is 200MHz, the model is SiT9102-200.00MHz, the system main clock for FPGA and used to generate DDR3 control clock; the other is 125MHz, model is SiT9102 -125MHz, reference clock input for GTP transceivers.

  • Page 9: Part 3.2: 148.5Mhz Active Differential Crystal

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Figure 3-2: 200Mhz Active Differential Crystal on the Core Board 200Mhz Differential Clock Pin Assignment Signal Name FPGA PIN SYS_CLK_P SYS_CLK_N Part 3.2: 148.5Mhz Active Differential Crystal G2 in Figure 3-3 is the 148.5Mhz active differential crystal, which is the reference input clock provided to the GTP module inside the FPGA.
  • Page 10 ARTIX-7 FPGA Development Board AX7C7100B User Manual Figure 3-3: 148.5Mhz Active Differential Crystal Schematic Figure 3-4: 1148.5Mhz Active Differential Crystal on the Core Board 125Mhz Differential Clock Pin Assignment Net Name FPGA PIN MGT_CLK0_P MGT_CLK0_N 10 / 30 Amazon Store: https://www.amazon.com/alinx...

  • Page 11: Part 4: Ddr3 Dram

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Part 4: DDR3 DRAM The FPGA core board AC7100B is equipped with two Micron 4Gbit (512MB) DDR3 chips, model MT41J256M16HA-125 (compatible with MT41K256M16HA-125). The DDR3 SDRAM has a maximum operating speed of 800MHz (data rate 1600Mbps). The DDR3 memory system is directly connected to the memory interface of the BANK 34 and BANK35 of the FPGA.
  • Page 12 ARTIX-7 FPGA Development Board AX7C7100B User Manual Figure 4-2: The DDR3 on the Core Board DDR3 DRAM pin assignment: Net Name FPGA PIN Name FPGA P/N DDR3_DQS0_P IO_L3P_T0_DQS_AD5P_35 DDR3_DQS0_N IO_L3N_T0_DQS_AD5N_35 DDR3_DQS1_P IO_L9P_T1_DQS_AD7P_35 DDR3_DQS1_N IO_L9N_T1_DQS_AD7N_35 DDR3_DQS2_P IO_L15P_T2_DQS_35 DDR3_DQS2_N IO_L15N_T2_DQS_35 DDR3_DQS3_P IO_L21P_T3_DQS_35...
  • Page 13 ARTIX-7 FPGA Development Board AX7C7100B User Manual DDR3_DQ [6] IO_L1P_T0_AD4P_35 DDR3_DQ [7] IO_L4P_T0_35 DDR3_DQ [8] IO_L11P_T1_SRCC_35 DDR3_DQ [9] IO_L11N_T1_SRCC_35 DDR3_DQ [10] IO_L8P_T1_AD14P_35 DDR3_DQ [11] IO_L10N_T1_AD15N_35 DDR3_DQ [12] IO_L7N_T1_AD6N_35 DDR3_DQ [13] IO_L10P_T1_AD15P_35 DDR3_DQ [14] IO_L7P_T1_AD6P_35 DDR3_DQ [15] IO_L12P_T1_MRCC_35 DDR3_DQ [16] IO_L18N_T2_35...
  • Page 14 ARTIX-7 FPGA Development Board AX7C7100B User Manual DDR3_A[6] IO_L5P_T0_34 DDR3_A[7] IO_L1P_T0_34 DDR3_A[8] IO_L2N_T0_34 DDR3_A[9] IO_L2P_T0_34 DDR3_A[10] IO_L5N_T0_34 DDR3_A[11] IO_L4P_T0_34 DDR3_A[12] IO_L4N_T0_34 DDR3_A[13] IO_L1N_T0_34 DDR3_A[14] IO_L6N_T0_VREF_34 DDR3_BA[0] IO_L9N_T1_DQS_34 DDR3_BA[1] IO_L9P_T1_DQS_34 DDR3_BA[2] IO_L11P_T1_SRCC_34 DDR3_S0 IO_L8P_T1_34 DDR3_RAS IO_L12P_T1_MRCC_34 DDR3_CAS IO_L12N_T1_MRCC_34 DDR3_WE IO_L7P_T1_34 DDR3_ODT...

  • Page 15: Part 5: Qspi Flash

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Part 5: QSPI Flash The FPGA core board AC7100B is equipped with one 128MBit QSPI FLASH, and the model is W25Q256FVEI, which uses the 3.3V CMOS voltage standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a boot device for the system to store the boot image of the system.
  • Page 16 ARTIX-7 FPGA Development Board AX7C7100B User Manual QSPI Flash pin assignments: Net Name FPGA PIN Name FPGA P/N QSPI_CLK CCLK_0 QSPI_CS IO_L6P_T0_FCS_B_14 QSPI_DQ0 IO_L1P_T0_D00_MOSI_14 QSPI_DQ1 IO_L1N_T0_D01_DIN_14 QSPI_DQ2 IO_L2P_T0_D02_14 QSPI_DQ3 IO_L2N_T0_D03_14 Figure 5-2: QSPI on the Core Board 16 / 30...

  • Page 17: Part 6: Led Light On Core Board

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Part 6: LED Light on Core Board There are 3 red LED lights on the AC7100B FPGA core board, one of which is the power indicator light (PWR), one is the configuration LED light (DONE), and one is the user LED light.

  • Page 18: Part 7: Reset Button

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Part 7: Reset Button There is a reset button on the AC7100B FPGA core board. The reset button is connected to the normal IO of the BANK34 of the FPGA chip. The user can use this reset button to initialize the FPGA program. When the button is pressed in the design, the signal voltage input to IO is low, and the reset signal is valid;...

  • Page 19: Part 8: Jtag Interface

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Part 8: JTAG Interface The JTAG test socket J1 is reserved on the AC7100B core board for JTAG download and debugging when the core board is used alone. Figure 8-1 is the schematic part of the JTAG port, which involves TMS, TDI, TDO, TCK. , GND, +3.3V these six signals.

  • Page 20: Part 9: Power Interface On The Core Board

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Part 9: Power Interface on the Core Board In order to make the AC7100B FPGA core board work alone, the core board is reserved with the 2PIN power interface (J3). When the user supplies power to the core board through 2PIN power interface (J3), it cannot be powered through the carrier board.

  • Page 21: Part 10: Board To Board Connectors Pin Assignment

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Part 10: Board to Board Connectors The core board has a total of four high-speed board to board connectors. The core board uses four 80-pin inter-board connectors to connect to the carrier board. The IO port of the FPGA is connected to the four connectors by differential routing.
  • Page 22 ARTIX-7 FPGA Development Board AX7C7100B User Manual PIN11 PIN12 PIN13 PIN14 PIN15 PIN16 B13_L4_P AA15 3.3V PIN17 PIN18 B13_L4_N AB15 3.3V PIN19 Ground PIN20 Ground PIN21 B13_L5_P 3.3V PIN22 B13_L1_P 3.3V PIN23 B13_L5_N AA14 3.3V PIN24 B13_L1_N AA16 3.3V PIN25...
  • Page 23 ARTIX-7 FPGA Development Board AX7C7100B User Manual Board to Board Connectors CON2 The 80-pin female connection header CON2 is used to extend the normal IO of the BANK13 and BANK14 of the FPGA. The voltage standards of both BANKs are 3.3V.
  • Page 24 ARTIX-7 FPGA Development Board AX7C7100B User Manual PIN49 Ground PIN50 Ground PIN51 B14_L5_N 3.3V PIN52 B14_L12_N 3.3V PIN53 B14_L5_P 3.3V PIN54 B14_L12_P 3.3V PIN55 B14_L18_N 3.3V PIN56 B14_L13_N 3.3V PIN57 B14_L18_P 3.3V PIN58 B14_L13_P 3.3V PIN59 Ground PIN60 Ground PIN61 B13_L17_P 3.3V...
  • Page 25 ARTIX-7 FPGA Development Board AX7C7100B User Manual PIN9 Ground PIN10 Ground PIN11 B15_L2_P 3.3V PIN12 B16_L23_P 3.3V PIN13 B15_L2_N 3.3V PIN14 B16_L23_N 3.3V PIN15 B15_L12_P 3.3V PIN16 B16_L22_P 3.3V PIN17 B15_L12_N 3.3V PIN18 B16_L22_N 3.3V PIN19 Ground PIN20 Ground PIN21 B15_L11_P 3.3V...
  • Page 26 ARTIX-7 FPGA Development Board AX7C7100B User Manual PIN73 B15_L24_N 3.3V PIN74 B15_L16_N 3.3V PIN75 PIN76 PIN77 FPGA_TCK 3.3V PIN78 FPGA_TDI 3.3V PIN79 FPGA_TDO 3.3V PIN80 FPGA_TMS 3.3V Board to Board Connectors CON4 The 80-Pin connector CON4 is used to extend the normal IO and GTP high-speed data and clock signals of the FPGA BANK16.
  • Page 27 ARTIX-7 FPGA Development Board AX7C7100B User Manual PIN31 MGT_TX1_N Differential PIN32 MGT_RX0_N Differential PIN33 Ground PIN34 Ground PIN35 MGT_RX1_P Differential PIN36 MGT_CLK1_P Differential PIN37 MGT_RX1_N Differential PIN38 MGT_CLK1_N Differential PIN39 Ground PIN40 Ground PIN41 B16_L5_P 3.3V PIN42 B16_L2_P 3.3V PIN43 B16_L5_N 3.3V...

  • Page 28: Part 11: Power Supply

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Part 11: Power Supply The AC7100B FPGA core board is powered by DC5V via carrier board, and it is powered by the J3 interface when it is used alone. Please be careful not to supply power by the J3 interface and the carrier board at the same time to avoid damage.
  • Page 29 MGTVCCAUX(+1.8V) GTP Transceiver Bank216 of FPGA Because the power supply of Artix-7 FPGA has the power-on sequence requirement, in the circuit design, we have designed according to the power requirements of the chip, and the power-on is 1.0V->1.8V->(1.5 V, 3.3V, VCCIO) and 1.0V->...

  • Page 30: Part 12: Structure Diagram

    ARTIX-7 FPGA Development Board AX7C7100B User Manual Part 12: Structure Diagram Figure 12-1: AC7100B FPGA Core board (Top view) Figure 12-2: AC7100B FPGA Core board (Bottom view) 30 / 30 Amazon Store: https://www.amazon.com/alinx...

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