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ARTIX-7 FPGA Development Board AX7A200 User Manual
Figure 3-2-1: Gigabit Ethernet Interface Schematic
Figure 3-3-2: Gigabit Ethernet interface on the Carrier board
Gigabit Ethernet Chip PHY pin assignments are as follows：
Signal Name
ETH_TXCK
ETH_TXD0
ETH_TXD1
ETH_TXD2
ETH_TXD3
ETH_TXCTL
ETH_RXCK
ETH_RXD0
ETH_RXD1
ETH_RXD2
ETH_RXD3
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FPGA Pin Number
P15
N14
P16
R17
R16
N17
V18
P19
U18
U17
P17
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Description
RGMII transmit clock
Transmit Data bit0
Transmit Data bit1
Transmit Data bit2
Transmit Data bit3
Transmit Enable Signal
RGMII Receive Clock
Receive Data Bit0
Receive Data Bit1
Receive Data Bit2
Receive Data Bit3
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