Part 2.5: Qspi Flash - Alinx AX7A200 Manual

ARTIX-7 FPGA Development Board AX7A200 User Manual
DDR3_A[12]
DDR3_A[13]
DDR3_A[14]
DDR3_BA[0]
DDR3_BA[1]
DDR3_BA[2]
DDR3_S0
DDR3_RAS
DDR3_CAS
DDR3_WE
DDR3_ODT
DDR3_RESET
DDR3_CLK_P
DDR3_CLK_N
DDR3_CKE

Part 2.5: QSPI Flash

The FPGA core board AC7A200 is equipped with one 128Mbit QSPI
FLASH, and the model is N25Q128, which uses the 3.3V CMOS voltage
standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a
boot device for the system to store the boot image of the system. These
images mainly include FPGA bit files, ARM application code, soft core
application code and other user data files. The specific models and related
parameters of SPI FLASH are shown in Table 2-5-1.
Position
U8
QSPI FLASH is connected to the dedicated pins of BANK0 and BANK14 of
the FPGA chip. The clock pin is connected to CCLK0 of BANK0, and other data
and chip select signals are connected to D00~D03 and FCS pins of BANK14
respectively. Figure 2-5-1 shows the hardware connection of QSPI Flash.
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IO_L4N_T0_34
IO_L1N_T0_34
IO_L6N_T0_VREF_34
IO_L9N_T1_DQS_34
IO_L9P_T1_DQS_34
IO_L11P_T1_SRCC_34
IO_L8P_T1_34
IO_L12P_T1_MRCC_34
IO_L12N_T1_MRCC_34
IO_L7P_T1_34
IO_L14N_T2_SRCC_34
IO_L15P_T2_DQS_34
IO_L3P_T0_DQS_34
IO_L3N_T0_DQS_34
IO_L14P_T2_SRCC_34
Model
N25Q128
Table 2-5-1: QSPI FLASH Specification
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Capacity
128M Bit Numonyx
https://www.amazon.com/alinx
Y2
U1
V3
AA3
Y3
Y4
AB3
V4
W4
AA1
U5
W6
R3
R2
T5
Factory