Part 2.7: Jtag Interface - Alinx AX7A200 Manual

ARTIX-7 FPGA Development Board AX7A200 User Manual
User LEDs Pin Assignment
Signal Name FPGA Pin Name
LED1 IO_L15N_T2_DQS_34

Part 2.7: JTAG Interface

The JTAG test socket J1 is reserved on the AC7A200 core board for JTAG
download and debugging when the core board is used alone. Figure 2-7-1 is
the schematic part of the JTAG port, which involves TMS, TDI, TDO, TCK. ,
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Figure 2-6-2: LED lights on the Core Board
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Sales Email:
FPGA Pin Number
W5
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rachel.zhou@aithtech.com
Description
User LED