Part 2.3: Active Differential Crystal - Alinx AX7A200 Manual

Xilinx artix-7 fpga

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Table of Contents

ARTIX-7 FPGA Development Board AX7A200 User Manual

DSP Slices

PCIe Gen2

GTP Transceiver

Speed Grade

Temperature Grade

FPGA power supply system

Artix-7 FPGA power supplies are V

. V

is the FPGA core power supply pin, which needs to be connected

MGTAVTT

CCINT

to 1.0V; V

is the power supply pin of FPGA Block RAM, connect to 1.0V;

CCBRAM

is FPGA auxiliary power supply pin, connect 1.8V; V

CCAUX

each BANK of FPGA, including BANK0, BANK13~16, BANK34~35. On

AC7A200 FPGA core board, BANK34 and BANK35 need to be connected to

DDR3, the voltage connection of BANK is 1.5V, and the voltage of other BANK

is 3.3V. The V

of BANK15 and BANK16 is powered by the LDO, and can be

CCO

changed by replacing the LDO chip. V

internal GTP transceiver, connected to 1.0V; V

of the GTP transceiver, connected to 1.2V.

The Artix-7 FPGA system requires that the power-up sequence be power

by V

, then V

CCINT

CCBRAM

same voltage, they can be powered up at the same time. The order of power

outages is reversed. The power-up sequence of the GTP transceiver is V

then V

, then V

MGTAVCC

can be powered up at the same time. The power-off sequence is just the

opposite of the power-on sequence.