Alinx AX7A200 Manual page 28

ARTIX-7 FPGA Development Board AX7A200 User Manual
Figure 2-9-2: Board to Board Connectors CON2 on the Core Board
Board to Board Connectors CON3
The 80-pin connector CON3 is used to extend the normal IO of the
BANK15 and BANK16 of the FPGA. In addition, four JTAG signals are also
connected to the carrier board via the CON3 connector. The voltage standards
of BANK15 and BANK16 can be adjusted by an LDO chip. The default installed
LDO is 3.3V. If you want to output other standard levels, you can replace it with
a suitable LDO.
Pin Assignment of Board to Board Connectors CON3
CON3 Net
PIN Name
PIN1 B15_IO0
PIN3 B16_IO0
PIN5 B15_L4_P
PIN7 B15_L4_N
PIN9 GND
PIN11 B15_L2_P
PIN13 B15_L2_N
PIN15 B15_L12_P
PIN17 B15_L12_N
PIN19 GND
PIN21 B15_L11_P
PIN23 B15_L11_N
PIN25 B15_L1_N
PIN27 B15_L1_P
PIN29 GND
PIN31 B15_L5_P
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FPGA Voltage CON3
PIN Level PIN
J16 3.3V PIN2
F15 3.3V PIN4
G17 3.3V PIN6
G18 3.3V PIN8
- Ground PIN10
G15 3.3V PIN12
G16 3.3V PIN14
J19 3.3V PIN16
H19 3.3V PIN18
- Ground PIN20
J20 3.3V PIN22
J21 3.3V PIN24
G13 3.3V PIN26
H13 3.3V PIN28
- Ground PIN30
J15 3.3V PIN32
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Net FPGA
Name
B15_IO25 M17
B16_IO25 F21
B16_L21_N A21
B16_L21_P
GND
B16_L23_P
B16_L23_N D21
B16_L22_P
B16_L22_N
GND
B16_L24_P
B16_L24_N
B15_L8_N
B15_L8_P
GND
B15_L7_N
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Voltage
PIN Level
3.3V
3.3V
3.3V
B21 3.3V
- Ground
E21 3.3V
3.3V
E22 3.3V
D22 3.3V
- Ground
G21 3.3V
G22 3.3V
G20 3.3V
H20 3.3V
- Ground
H22 3.3V