Alinx AX7A200 Manual page 17

ARTIX-7 FPGA Development Board AX7A200 User Manual
Figure 2-4-2: The DDR3 on the Core Board
DDR3 DRAM pin assignment:
Net Name
DDR3_DQS0_P
DDR3_DQS0_N
DDR3_DQS1_P
DDR3_DQS1_N
DDR3_DQS2_P
DDR3_DQS2_N
DDR3_DQS3_P
DDR3_DQS3_N
DDR3_DQ[0]
DDR3_DQ [1]
DDR3_DQ [2]
DDR3_DQ [3]
DDR3_DQ [4]
DDR3_DQ [5]
DDR3_DQ [6]
DDR3_DQ [7]
DDR3_DQ [8]
DDR3_DQ [9]
DDR3_DQ [10]
DDR3_DQ [11]
17 / 59
FPGA PIN Name
IO_L3P_T0_DQS_AD5P_35
IO_L3N_T0_DQS_AD5N_35
IO_L9P_T1_DQS_AD7P_35
IO_L9N_T1_DQS_AD7N_35
IO_L15P_T2_DQS_35
IO_L15N_T2_DQS_35
IO_L21P_T3_DQS_35
IO_L21N_T3_DQS_35
IO_L2P_T0_AD12P_35
IO_L5P_T0_AD13P_35
IO_L1N_T0_AD4N_35
IO_L6P_T0_35
IO_L2N_T0_AD12N_35
IO_L5N_T0_AD13N_35
IO_L1P_T0_AD4P_35
IO_L4P_T0_35
IO_L11P_T1_SRCC_35
IO_L11N_T1_SRCC_35
IO_L8P_T1_AD14P_35
IO_L10N_T1_AD15N_35
Amazon Store: https://www.amazon.com/alinx
Sales Email: rachel.zhou@aithtech.com
FPGA P/N
E1
D1
K2
J2
M1
L1
P5
P4
C2
G1
A1
F3
B2
F1
B1
E2
H3
G3
H2
H5