Alinx ARTIX-7 FPGA User Manual
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Alinx ARTIX-7 FPGA User Manual

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ARTIX-7 FPGA
Development Board
AX7103
User Manual

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Summary of Contents for Alinx ARTIX-7 FPGA

  • Page 1 ARTIX-7 FPGA Development Board AX7103 User Manual...

  • Page 2: Version Record

    ARTIX-7 FPGA Development Board AX7103 User Manual Version Record Version Date Release By Description Rev 1.2 2020-10-30 Rachel Zhou First Release www.alinx.com 2 / 55...

  • Page 3: Table Of Contents

    ARTIX-7 FPGA Development Board AX7103 User Manual Table of Contents Version Record.......................2 Part 1: FPGA Development Board Introduction..........6 Part 2: AC7100B core board................9 Part 2.1: AC7100B Core Board Introduction..........9 Part 2.2: FPGA Chip..................11 Part 2.3: Active Differential Crystal............12 Part 2.4: DDR3 DRAM................
  • Page 4 ARTIX-7 FPGA Development Board AX7103 User Manual Part 3.12: keys..................... 51 Part 3.13: LED Light................... 52 Part 3.14: Power Supply................53 www.alinx.com 4 / 55...
  • Page 5 Output interface, 1 HDMI Input interface, Uart Interface, SD card slot etc. It meets user's requirements for PCIe high-speed data exchange, video transmission processing and industrial control. It is a "Versatile" ARTIX-7 FPGA development platform. It provides the possibility for high-speed video transmission, pre-validation and post-application of network and fiber communication and data processing.

  • Page 6: Part 1: Fpga Development Board Introduction

    ARTIX-7 FPGA Development Board AX7103 User Manual Part 1: FPGA Development Board Introduction The entire structure of the AX7103 FPGA development board is inherited from our consistent core board + carrier board model. A high-speed inter-board connector is used between the core board and the carrier board.
  • Page 7 ARTIX-7 FPGA Development Board AX7103 User Manual Figure 1-1-1: The Schematic Diagram of the AX7103 Through this diagram, you can see the interfaces and functions that the AX7103 FPGA Development Board contains:  Artix-7 FPGA core board The core board consists of XC7A100T + 8Gb DDR3 + 128Mb QSPI FLASH.
  • Page 8 ARTIX-7 FPGA Development Board AX7103 User Manual KSZ9031RNX chip supports 10/100/1000 Mbps network transmission rates; full duplex and adaptive.  1-channel HDMI Output interface Silion Image's SIL9134 HDMI encoding chip is selected to support up to 1080P@60Hz output and support 3D output.

  • Page 9: Part 2: Ac7100B Core Board

    ARTIX-7 FPGA Development Board AX7103 User Manual Part 2: AC7100B core board Part 2.1: AC7100B Core Board Introduction AC7100B (core board model, the same below) FPGA core board, it is based on XILINX's ARTIX-7 series 100T XC7A100T-2FGG484I. It is a high-performance core board with high speed, high bandwidth and high capacity.
  • Page 10 ARTIX-7 FPGA Development Board AX7103 User Manual Figure 2-1-1: AC7100B Core Board (Front View) Figure 2-1-2: AC7100B Core Board (Rear View) www.alinx.com 10 / 55...

  • Page 11: Part 2.2: Fpga Chip

    Xilinx's Artix-7 series. The speed grade is 2, and the temperature grade is industry grade. This model is a FGG484 package with 484 pins. Xilinx ARTIX-7 FPGA chip naming rules as below Figure 2-2-1: The Specific Chip Model Definition of ARTIX-7 Series...

  • Page 12: Part 2.3: Active Differential Crystal

    FPGA internal GTP transceiver, connected to 1.0V; VMGTAVTT is the termination voltage of the GTP transceiver, connected to 1.2V. The Artix-7 FPGA system requires that the power-up sequence be powered by VCCINT, then VCCBRAM, then VCCAUX, and finally VCCO. If VCCINT and VCCBRAM have the same voltage, they can be powered up at the same time.
  • Page 13 ARTIX-7 FPGA Development Board AX7103 User Manual BANK34 global clock pin MRCC (R4 and T4) of the FPGA. This 200Mhz differential clock can be used to drive the user logic in the FPGA. Users can configure the PLLs and DCMs inside the FPGA to generate clocks of different frequencies.
  • Page 14 ARTIX-7 FPGA Development Board AX7103 User Manual output is connected to the GTP BANK216 clock pins MGTREFCLK0P (F6) and MGTREFCLK0N (E6) of the FPGA. Figure 2-3-3: 125Mhz Active Differential Crystal Schematic Figure 2-3-4: 125Mhz Active Differential Crystal on the Core Board...

  • Page 15: Part 2.4: Ddr3 Dram

    ARTIX-7 FPGA Development Board AX7103 User Manual Part 2.4: DDR3 DRAM The FPGA core board AC7100B is equipped with two Micron 4Gbit (512MB) DDR3 chips, model MT41J256M16HA-125 (compatible with MT41K256M16HA-125). The DDR3 SDRAM has a maximum operating speed of 800MHz (data rate 1600Mbps). The DDR3 memory system is directly connected to the memory interface of the BANK 34 and BANK35 of the FPGA.
  • Page 16 ARTIX-7 FPGA Development Board AX7103 User Manual Figure 2-4-2: The DDR3 on the Core Board DDR3 DRAM pin assignment: Net Name FPGA PIN Name FPGA P/N DDR3_DQS0_P IO_L3P_T0_DQS_AD5P_35 DDR3_DQS0_N IO_L3N_T0_DQS_AD5N_35 DDR3_DQS1_P IO_L9P_T1_DQS_AD7P_35 DDR3_DQS1_N IO_L9N_T1_DQS_AD7N_35 DDR3_DQS2_P IO_L15P_T2_DQS_35 DDR3_DQS2_N IO_L15N_T2_DQS_35 DDR3_DQS3_P IO_L21P_T3_DQS_35...

  • Page 17: Part 2.5: Qspi Flash

    ARTIX-7 FPGA Development Board AX7103 User Manual DDR3_DQ [4] IO_L2N_T0_AD12N_35 DDR3_DQ [5] IO_L5N_T0_AD13N_35 DDR3_DQ [6] IO_L1P_T0_AD4P_35 DDR3_DQ [7] IO_L4P_T0_35 DDR3_DQ [8] IO_L11P_T1_SRCC_35 DDR3_DQ [9] IO_L11N_T1_SRCC_35 DDR3_DQ [10] IO_L8P_T1_AD14P_35 DDR3_DQ [11] IO_L10N_T1_AD15N_35 DDR3_DQ [12] IO_L7N_T1_AD6N_35 DDR3_DQ [13] IO_L10P_T1_AD15P_35 DDR3_DQ [14] IO_L7P_T1_AD6P_35...
  • Page 18 ARTIX-7 FPGA Development Board AX7103 User Manual the FPGA chip. The clock pin is connected to CCLK0 of BANK0, and other data and chip select signals are connected to D00~D03 and FCS pins of BANK14 respectively. Figure 2-5-1 shows the hardware connection of QSPI Flash.

  • Page 19: Part 2.6: Led Light On Core Board

    ARTIX-7 FPGA Development Board AX7103 User Manual Part 2.6: LED Light on Core Board There are 3 red LED lights on the AC7100B FPGA core board, one of which is the power indicator light (PWR), one is the configuration LED light (DONE), and one is the user LED light.

  • Page 20: Part 2.8: Jtag Interface

    ARTIX-7 FPGA Development Board AX7103 User Manual the reset key connection is shown in Figure 2-7-1: Figure 2-7-1: Reset key Schematic Figure 2-7-2: Reset key on the Core Board Reset key pin assignment Signal Name ZYNQ Pin Name ZYNQ Pin Number...

  • Page 21: Part 2.9: Power Interface On The Core Board

    ARTIX-7 FPGA Development Board AX7103 User Manual The JTAG interface J1 on AC7100B FPGA core board uses a 6-pin 2.54mm pitch single-row test hole. If you need to use the JTAG connection to debug on the core board, you need to solder a 6-pin single-row pin header.

  • Page 22: Part 2.10: Board To Board Connectors Pin Assignment

    ARTIX-7 FPGA Development Board AX7103 User Manual Figure 2-9-2：J3 interface on the Core Board Part 2.10: Board to Board Connectors pin assignment The core board has a total of four high-speed board to board connectors. The core board uses four 80-pin inter-board connectors to connect to the carrier board.
  • Page 23 ARTIX-7 FPGA Development Board AX7103 User Manual Pin Assignment of Board to Board Connectors CON1 CON1 Signal Name FPGA Pin Voltage CON1 Signal Name FPGA Pin Voltage Level Level PIN1 VCCIN PIN2 VCCIN PIN3 VCCIN PIN4 VCCIN PIN5 VCCIN PIN6...
  • Page 24 ARTIX-7 FPGA Development Board AX7103 User Manual PIN59 Ground PIN60 Ground PIN61 B16_L1_N 3.3V PIN62 PIN63 B16_L1_P 3.3V PIN64 PIN65 B16_L4_N 3.3V PIN66 PIN67 B16_L4_P 3.3V PIN68 PIN69 Ground PIN70 Ground PIN71 B16_L6_N 3.3V PIN72 Board to Board Connectors CON2 The 80-pin female connection header CON2 is used to extend the normal IO of the BANK13 and BANK14 of the FPGA.
  • Page 25 ARTIX-7 FPGA Development Board AX7103 User Manual PIN33 B13_L9_P AA10 3.3V PIN34 B13_IO0 3.3V PIN35 B13_L8_N AB10 3.3V PIN36 B14_L7_N 3.3V PIN37 B13_L8_P 3.3V PIN38 B14_L7_P 3.3V PIN39 Ground PIN40 Ground PIN41 B14_L11_N 3.3V PIN42 B14_L4_P 3.3V PIN43 B14_L11_P 3.3V...
  • Page 26 ARTIX-7 FPGA Development Board AX7103 User Manual a suitable LDO. Pin Assignment of Board to Board Connectors CON3 CON1 Signal Name FPGA CON1 Signal Name FPGA Pin Voltage Voltage Level Level PIN1 B15_IO0 3.3V PIN2 B15_IO25 3.3V PIN3 B16_IO0 3.3V...
  • Page 27 ARTIX-7 FPGA Development Board AX7103 User Manual PIN57 B15_L21_N 3.3V PIN58 B15_L10_N 3.3V PIN59 Ground PIN60 Ground PIN61 B15_L23_P 3.3V PIN62 B15_L18_P 3.3V PIN63 B15_L23_N 3.3V PIN64 B15_L18_N 3.3V PIN65 B15_L22_P 3.3V PIN66 B15_L17_N 3.3V PIN67 B15_L22_N 3.3V PIN68 B15_L17_P 3.3V...
  • Page 28 ARTIX-7 FPGA Development Board AX7103 User Manual PIN15 Ground PIN16 Ground PIN17 MGT_TX3_P Differential PIN18 MGT_RX2_P Differential PIN19 MGT_TX3_N Differential PIN20 MGT_RX2_N Differential PIN21 Ground PIN22 Ground PIN23 MGT_RX3_P Differential PIN24 MGT_TX0_P Differential PIN25 MGT_RX3_N Differential PIN26 MGT_TX0_N Differential PIN27...

  • Page 29: Part 2.11: Power Supply

    ARTIX-7 FPGA Development Board AX7103 User Manual PIN79 PIN80 Part 2.11: Power Supply The AC7100B FPGA core board is powered by DC5V via carrier board, and it is powered by the J3 interface when it is used alone. Please be careful not to supply power to J3 interface and the carrier board at the same time to avoid damage.
  • Page 30 MGTVCCAUX(+1.8V) GTP Transceiver Bank216 of FPGA Because the power supply of Artix-7 FPGA has the power-on sequence requirement, in the circuit design, we have designed according to the power requirements of the chip, and the power-on is 1.0V->1.8V->(1.5 V, 3.3V, VCCIO) and 1.0V->...

  • Page 31: Part 2.12: Structure Diagram

    ARTIX-7 FPGA Development Board AX7103 User Manual Part 2.12: Structure Diagram Figure 2-12-1: AC7100B FPGA Core board (Top view) Figure 2-12-2: AC7100B FPGA Core board (Bottom view) www.alinx.com 31 / 55...

  • Page 32: Part 3: Carrier Board

    ARTIX-7 FPGA Development Board AX7103 User Manual Part 3: Carrier board Part 3.1: Carrier board Introduction Through the previous function introduction, you can understand the function of the carrier board part  1-channel PCIe x4 high speed data transmission interface ...

  • Page 33: Part 3.2: Gigabit Ethernet Interface

    ARTIX-7 FPGA Development Board AX7103 User Manual Part 3.2: Gigabit Ethernet Interface The AX7103 FPGA development board provides users with 2-channel Gigabit network communication service through the Micrel KSZ9031RNX Ethernet PHY chip. The KSZ9031RNX chip supports 10/100/1000 Mbps network transmission rate and communicates with the FPGA through the GMII interface.
  • Page 34 ARTIX-7 FPGA Development Board AX7103 User Manual sampled on the rising edge of the clock. Figure 3-2-1: Gigabit Ethernet Interface Schematic Figure 3-3-2: Gigabit Ethernet interface on the Carrier board www.alinx.com 34 / 55...
  • Page 35 ARTIX-7 FPGA Development Board AX7103 User Manual Gigabit Ethernet Chip PHY1 pin assignments are as follows： Signal Name FPGA Pin Number Description E1_GTXC PHY1 RGMII transmit clock E1_TXD0 PHY1 Transmit Data bit0 E1_TXD1 PHY1 Transmit Data bit1 E1_TXD2 PHY1 Transmit Data bit2...

  • Page 36: Part 3.3: Pcie X4 Interface

    ARTIX-7 FPGA Development Board AX7103 User Manual Part 3.3: PCIe x4 Interface The AX7103 FPGA development board provides an industrial-grade high-speed data transfer PCIe x4 interface. The PCIE card interface conforms to the standard PCIe card electrical specifications and can be used directly on the x4 PCIe slot of a normal PC.
  • Page 37 ARTIX-7 FPGA Development Board AX7103 User Manual Figure 3-3-2: PCIex4 on the Carrier board PCIex4 Interface Pin Assignment: Signal Name FPGA Pin Description PCIE_RX0_P PCIE Channel 0 Data Receive Positive PCIE_RX0_N PCIE Channel 0 Data Receive Negative PCIE_RX1_P PCIE Channel 1 Data Receive Positive...

  • Page 38: Part 3.4: Hdmi Output Interface

    ARTIX-7 FPGA Development Board AX7103 User Manual Part 3.4: HDMI output interface HDMI output interface, select Silion Image's SIL9134 HDMI (DVI) encoding chip, support up to 1080P@60Hz output, support 3D output. The IIC configuration interface of SIL9134 is also connected to the IO of the FPGA.
  • Page 39 ARTIX-7 FPGA Development Board AX7103 User Manual HDMI Input Pin Assignment: Signal Name FPGA Pin 9134_nRESET 9134_CLK 9134_HS 9134_VS 9134_DE 9134_D[0] 9134_D[1] 9134_D[2] 9134_D[3] 9134_D[4] 9134_D[5] 9134_D[6] 9134_D[7] 9134_D[8] 9134_D[9] 9134_D[10] 9134_D[11] 9134_D[12] 9134_D[13] 9134_D[14] 9134_D[15] 9134_D[16] 9134_D[17] 9134_D[18] 9134_D[19]...

  • Page 40: Part 3.5: Hdmi Input Interface

    ARTIX-7 FPGA Development Board AX7103 User Manual Part 3.5: HDMI Input interface HDMI output interface, select Silion Image's SIL9013 HDMI decoder chip, support up to 1080P@60Hz input and support data output in different formats. The IIC configuration interface of the SIL9013 is connected to the IO of the FPGA.
  • Page 41 ARTIX-7 FPGA Development Board AX7103 User Manual HDMI Input Pin Assignment: Signal Name FPG Pin Number 9013_nRESET 9013_CLK 9013_HS 9013_VS 9013_DE 9013_D[0] 9013_D[1] 9013_D[2] 9013_D[3] 9013_D[4] 9013_D[5] 9013_D[6] 9013_D[7] 9013_D[8] 9013_D[9] 9013_D[10] 9013_D[11] 9013_D[12] 9013_D[13] 9013_D[14] 9013_D[15] 9013_D[16] 9013_D[17] 9013_D[18]...

  • Page 42: Part 3.6: Sd Card Slot

    ARTIX-7 FPGA Development Board AX7103 User Manual Part 3.6: SD Card Slot The SD card (Secure Digital Memory Card) is a memory card based on the semiconductor flash memory process. It was completed in 1999 by the Japanese Panasonic-led concept, and the participants Toshiba and SanDisk of the United States conducted substantial research and development.

  • Page 43: Part 3.7: Usb To Serial Port

    ARTIX-7 FPGA Development Board AX7103 User Manual Figure 3-6-2: SD Card Slot on the Carrier board SD card slot pin assignment: SD Mode Signal Name FPGA PIN SD_CLK AB12 SD_CMD AB11 SD_CD_N SD_DAT0 AA13 SD_DAT1 AB13 SD_DAT2 SD_DAT3 AA14 Part 3.7: USB to Serial Port The AX7103 FPGA development board includes the USB-UAR chip of Silicon Labs CP2102GM.
  • Page 44 ARTIX-7 FPGA Development Board AX7103 User Manual Figure 3-7-1: USB to serial port schematic Figure 3-7-2: USB to serial port on the Carrier board Two LED indicators (LED3 and LED4) are set for the serial port signal, and the silkscreen on the PCB is TX and RX, indicating that the serial port has data...

  • Page 45: Part 3.8: Eeprom 24Lc04

    ARTIX-7 FPGA Development Board AX7103 User Manual USB to serial port pin assignment: Signal Name FPGA PIN UART1_RXD UART1_TXD Part 3.8: EEPROM 24LC04 AX7013 carrier board contains an EEPROM, model 24LC04, and has a capacity of 4Kbit (2*256*8bit). It consists of two 256-byte blocks and communicates via the IIC bus.

  • Page 46: Part 3.9: Expansion Header

    Part 3.9: Expansion Header The carrier board is reserved with two 0.1inch spacing standard 40-pin expansion ports J11 and J13, which are used to connect the ALINX modules or the external circuit designed by the user. The expansion port has 40 signals, of which 1-channel 5V power supply, 2-channel 3.3 V power supply, 3-channle...
  • Page 47 ARTIX-7 FPGA Development Board AX7103 User Manual The figure 3-9-2 detailed the J4 expansion port on the carrier board. The Pin1 and Pin2 of the expansion port are already marked on the board. Figure 3-9-2: Expansion header J11 on the Carrier board...
  • Page 48 ARTIX-7 FPGA Development Board AX7103 User Manual Figure 3-9-3: Expansion header J13 schematic The figure 3-9-4 detailed the J13 expansion port on the carrier board. The Pin1 and Pin2 of the expansion port are already marked on the board. Figure 3-9-4: Expansion header J13 on the carrier board...

  • Page 49: Part 3.10: Jtag Interface

    ARTIX-7 FPGA Development Board AX7103 User Manual AB21 AB22 AA21 AA20 AB20 AA19 AA18 AB18 +3.3V +3.3V Part 3.10: JTAG Interface A JTAG interface is reserved on the AX7103 FPGA carrier board for downloading FPGA programs or firmware to FLASH. In order to prevent...

  • Page 50: Part 3.11: Xadc Interface (Not Installed By Default)

    ARTIX-7 FPGA Development Board AX7103 User Manual Figure 3-10-2: JTAG Interface on the carrier board Be careful not to hot swap when JTAG cable is plugged and unplugged. Part 3.11: XADC interface (not installed by default) The AX7103 carrier board has an extended XADC connector interface, and the connector uses a 2x8 0.1inch pitch double-row pin.
  • Page 51 ARTIX-7 FPGA Development Board AX7103 User Manual Figure 3-11-2: XADC Connector Schematic Figure 3-11-3: XADC Connector on the Carrier board XADC Pin Assignment XADC FPGA Pin Input amplitude Description Interface VP_0 : L10 Peak to peak 1V FPGA-specific XADC input channel 1，2...
  • Page 52 ARTIX-7 FPGA Development Board AX7103 User Manual Figure 3-12-1: key Schematic Figure 3-13-2: Two keys on the Carrier board keys Pin Assignment Net Name FPGA PIN KEY1 KEY2 Part 3.13: LED Light There are seven red LEDs on the AX7103 FPGA carrier board, one of which is the power indicator (PWR), two are USB Uart data receiving and transmitting indicators, and four are users LED lights (LED1~LED4).
  • Page 53 ARTIX-7 FPGA Development Board AX7103 User Manual schematic diagram of the user LEDs hardware connection is shown in Figure 3-13-1. Figure 3-13-1: The User LEDs Schematic Figure 3-13-2: The User LEDs on the Carrier board Pin assignment of user LED lights...
  • Page 54 ARTIX-7 FPGA Development Board AX7103 User Manual Figure 3-14-1: Power supply method for AX7103 FPGA Board The FPGA carrier board converts the +12V voltage into +5V, +3.3V, +1.8V and +1.2V four-way power supply through the 4-channel DC/DC power supply chip MP1482. In addition, the +5V power supply on the FPGA carrier board supplies power to the AC7100B FPGA core board through the inter-board connector.
  • Page 55 ARTIX-7 FPGA Development Board AX7103 User Manual Figure 3-14-3: Power Supply Circuit on the Carrier board www.alinx.com 55 / 55...

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