Alinx AX7A200 Manual page 14

ARTIX-7 FPGA Development Board AX7A200 User Manual
model is SiT9102 -125MHz, reference clock input for GTP transceivers.
Part 2.3.1: 200Mhz Active Differential clock
G1 in Figure 2-3-1 is the 200M active differential crystal that provides the
development board system clock source. The crystal output is connected to the
BANK34 global clock pin MRCC (R4 and T4) of the FPGA. This 200Mhz
differential clock can be used to drive the user logic in the FPGA. Users can
configure the PLLs and DCMs inside the FPGA to generate clocks of different
frequencies.
Figure 2-3-1: 200Mhz Active Differential Crystal Schematic
Figure 2-3-2: 200Mhz Active Differential Crystal on the Core Board
200Mhz Differential Clock Pin Assignment
Signal Name
SYS_CLK_P
SYS_CLK_N
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FPGA PIN
R4
T4