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16.3 Clock Settings
16.3.1 I2C Operating Clock
Master mode operating clock
When using the I2C Ch.n in master mode, the I2C Ch.n operating clock CLK_I2Cn must be supplied to the I2C
Ch.n from the clock generator. The CLK_I2Cn supply should be controlled as in the procedure shown below.
1. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the "Power Supply,
Reset, and Clocks" chapter).
2. Set the following I2C_nCLK register bits:
- I2C_nCLK.CLKSRC[1:0] bits (Clock source selection)
- I2C_nCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting)
When using the I2C in master mode during SLEEP mode, the I2C Ch.n operating clock CLK_I2Cn must be
configured so that it will keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_I2Cn clock
source.
The I2C operating clock should be selected so that the baud rate generator will be configured easily.
Slave mode operating clock
The I2C set to slave mode uses the SCL supplied from the I
by the I2C_nCLK register is ineffective.
The I2C keeps operating using the clock supplied from the external I
halt during SLEEP mode, so the I2C can receive data and can generate receive buffer full interrupts.
16.3.2 Clock Supply During Debugging
In master mode, the CLK_I2Cn supply during debugging should be controlled using the I2C_nCLK.DBRUN bit.
The CLK_I2Cn supply to the I2C Ch.n is suspended when the CPU enters debug state if the I2C_nCLK.DBRUN
bit = 0. After the CPU returns to normal operation, the CLK_I2Cn supply resumes. Although the I2C Ch.n stops
operating when the CLK_I2Cn supply is suspended, the output pin and registers retain the status before debug state
was entered. If the I2C_nCLK.DBRUN bit = 1, the CLK_I2Cn supply is not suspended and the I2C Ch.n will keep
operating in debug state.
In slave mode, the I2C Ch.n operates with the external I
whether the CPU is placed into debug state or normal operation state.
16.3.3 Baud Rate Generator
The I2C includes a baud rate generator to generate the serial clock SCL used in master mode. The I2C set to slave
mode does not use the baud rate generator, as it operates with the serial clock input from the SCLn pin.
Setting data transfer rate (for master mode)
The transfer rate is determined by the I2C_nBR.BRT[6:0] bit settings. Use the following equations to calculate
the setting values for obtaining the desired transfer rate.
f
CLK_I2Cn
bps = — — — — — — — — —
(BRT + 3) × 2
Where
bps:
Data transfer rate [bit/s]
f
: I2C operating clock frequency [Hz]
CLK_I2Cn
BRT:
I2C_nBR.BRT[6:0] bits setting value (1 to 127)
* The equations above do not include SCL rising/falling time and delay time by clock stretching (see Fig-
ure 16.3.3.1).
Note: The I
C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do
2
not set a transfer rate exceeding the limit.
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
C master as its operating clock. The clock setting
2
C master clock input from the SCLn pin regardless of
2
BRT = — — — — — — — - 3
Seiko Epson Corporation
C master even if all the internal clocks
2
f
CLK_I2Cn
bps × 2
16 I
2
C (I2C)
(Eq. 16.1)
16-3
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