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Peripheral circuit
UART (UART3) Ch.2
16-bit timer (T16) Ch.6
Synchronous serial interface
(SPIA) Ch.1
16-bit timer (T16) Ch.2
Quad synchronous serial
interface (QSPI) Ch.0
I
C (I2C) Ch.1
2
I
C (I2C) Ch.2
2
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Address
0x0020 062a UART3_2RXD
0x0020 062c UART3_2INTF
0x0020 062e UART3_2INTE
0x0020 0630 UART3_2
TBEDMAEN
0x0020 0632 UART3_2
RB1FDMAEN
0x0020 0634 UART3_2CAWF
0x0020 0660 T16_6CLK
0x0020 0662 T16_6MOD
0x0020 0664 T16_6CTL
0x0020 0666 T16_6TR
0x0020 0668 T16_6TC
0x0020 066a T16_6INTF
0x0020 066c T16_6INTE
0x0020 0670 SPIA_1MOD
0x0020 0672 SPIA_1CTL
0x0020 0674 SPIA_1TXD
0x0020 0676 SPIA_1RXD
0x0020 0678 SPIA_1INTF
0x0020 067a SPIA_1INTE
0x0020 067c SPIA_1TBEDMAEN SPIA Ch.1 Transmit Buffer Empty DMA Request Enable Register
0x0020 067e SPIA_1RBFDMAEN SPIA Ch.1 Receive Buffer Full DMA Request Enable Register
0x0020 0680 T16_2CLK
0x0020 0682 T16_2MOD
0x0020 0684 T16_2CTL
0x0020 0686 T16_2TR
0x0020 0688 T16_2TC
0x0020 068a T16_2INTF
0x0020 068c T16_2INTE
0x0020 0690 QSPI_0MOD
0x0020 0692 QSPI_0CTL
0x0020 0694 QSPI_0TXD
0x0020 0696 QSPI_0RXD
0x0020 0698 QSPI_0INTF
0x0020 069a QSPI_0INTE
0x0020 069c QSPI_0TBEDMAEN QSPI Ch.0 Transmit Buffer Empty DMA Request Enable Register
0x0020 069e QSPI_0RBFDMAEN QSPI Ch.0 Receive Buffer Full DMA Request Enable Register
0x0020 06a0 QSPI_0FRLDMAEN QSPI Ch.0 FIFO Data Ready DMA Request Enable Register
0x0020 06a2 QSPI_0MMACFG1
0x0020 06a4 QSPI_0RMADRH
0x0020 06a6 QSPI_0MMACFG2
0x0020 06a8 QSPI_0nMB
0x0020 06c0 I2C_1CLK
0x0020 06c2 I2C_1MOD
0x0020 06c4 I2C_1BR
0x0020 06c8 I2C_1OADR
0x0020 06ca I2C_1CTL
0x0020 06cc I2C_1TXD
0x0020 06ce I2C_1RXD
0x0020 06d0 I2C_1INTF
0x0020 06d2 I2C_1INTE
0x0020 06d4 I2C_1TBEDMAEN
0x0020 06d6 I2C_1RBFDMAEN
0x0020 06e0 I2C_2CLK
0x0020 06e2 I2C_2MOD
0x0020 06e4 I2C_2BR
0x0020 06e8 I2C_2OADR
0x0020 06ea I2C_2CTL
0x0020 06ec I2C_2TXD
0x0020 06ee I2C_2RXD
0x0020 06f0 I2C_2INTF
0x0020 06f2 I2C_2INTE
0x0020 06f4 I2C_2TBEDMAEN
0x0020 06f6 I2C_2RBFDMAEN
Seiko Epson Corporation
Register name
UART3 Ch.2 Receive Data Register
UART3 Ch.2 Status and Interrupt Flag Register
UART3 Ch.2 Interrupt Enable Register
UART3 Ch.2 Transmit Buffer Empty DMA Request Enable Register
UART3 Ch.2 Receive Buffer One Byte Full DMA Request Enable
Register
UART3 Ch.2 Carrier Waveform Register
T16 Ch.6 Clock Control Register
T16 Ch.6 Mode Register
T16 Ch.6 Control Register
T16 Ch.6 Reload Data Register
T16 Ch.6 Counter Data Register
T16 Ch.6 Interrupt Flag Register
T16 Ch.6 Interrupt Enable Register
SPIA Ch.1 Mode Register
SPIA Ch.1 Control Register
SPIA Ch.1 Transmit Data Register
SPIA Ch.1 Receive Data Register
SPIA Ch.1 Interrupt Flag Register
SPIA Ch.1 Interrupt Enable Register
T16 Ch.2 Clock Control Register
T16 Ch.2 Mode Register
T16 Ch.2 Control Register
T16 Ch.2 Reload Data Register
T16 Ch.2 Counter Data Register
T16 Ch.2 Interrupt Flag Register
T16 Ch.2 Interrupt Enable Register
QSPI Ch.0 Mode Register
QSPI Ch.0 Control Register
QSPI Ch.0 Transmit Data Register
QSPI Ch.0 Receive Data Register
QSPI Ch.0 Interrupt Flag Register
QSPI Ch.0 Interrupt Enable Register
QSPI Ch.0 Memory Mapped Access Configuration Register 1
QSPI Ch.0 Remapping Start Address High Register
QSPI Ch.0 Memory Mapped Access Configuration Register 2
QSPI Ch.0 Mode Byte Register
I2C Ch.1 Clock Control Register
I2C Ch.1 Mode Register
I2C Ch.1 Baud-Rate Register
I2C Ch.1 Own Address Register
I2C Ch.1 Control Register
I2C Ch.1 Transmit Data Register
I2C Ch.1 Receive Data Register
I2C Ch.1 Status and Interrupt Flag Register
I2C Ch.1 Interrupt Enable Register
I2C Ch.1 Transmit Buffer Empty DMA Request Enable Register
I2C Ch.1 Receive Buffer Full DMA Request Enable Register
I2C Ch.2 Clock Control Register
I2C Ch.2 Mode Register
I2C Ch.2 Baud-Rate Register
I2C Ch.2 Own Address Register
I2C Ch.2 Control Register
I2C Ch.2 Transmit Data Register
I2C Ch.2 Receive Data Register
I2C Ch.2 Status and Interrupt Flag Register
I2C Ch.2 Interrupt Enable Register
I2C Ch.2 Transmit Buffer Empty DMA Request Enable Register
I2C Ch.2 Receive Buffer Full DMA Request Enable Register
4 MEMORY AND BUS
4-7
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